AVX2 elementwise GEMM performs a misaligned typed BF16 load under UBSan

[VikashLoomba]

Row: KERNEL-GEMM-CPU-ELEM-X86WIDE

Observed

The address/undefined-sanitizer lane for PR #2856 reached undefined behavior in the AVX2 elementwise GEMM at merge ref 65c96d71ec4ef467119736e79560541cc01bd403:

src/vt/cpu/cpu_matmul_elem_avx2.cpp:231: runtime error:
load of misaligned address ...3745 for type 'const T', which requires 2 byte alignment
#0 BtM4Avx2<(vt::cpu::ElemKind)2>
#1 MatmulOneChunk<true>

The failing addresses are odd, so this is not merely the sanitizer asking for wider SIMD alignment. Constructing the typed T lvalue is already invalid before ElemA<K>::Cvt widens it.

The same report made these three binaries fail:

• test_dots3_note_vision
• test_dots3_note_audio
• test_openai_api_server_dots3_mm_forward

The ordinary CPU lane ran the same 729-test tree without these three failures, so the defect is sanitizer-visible rather than a normal assertion failure.

Attribution

PR #2856 changes no CPU GEMM, Dots3, API-server, or tensor-layout path. Its complete diff is one ROCm evidence spec, two oracle scripts, one script test, four NumPy arrays, one manifest, and comments in the Qwen3.5 sacred test.

git blame assigns the invalid load to the original AVX2 tier commit ea89926f58. Current main 41b6aa2560a576c28fa15f2a3ff4505305f9b850 still carries it.

Owed

The KERNEL-GEMM-CPU-ELEM-X86WIDE row owns the AVX2 load and its tier-forcing gate. Repair the load without imposing an alignment precondition that tensor views do not guarantee, and add a focused odd-byte-offset sanitizer case that reaches the production MatmulBT dispatch. Preserve the row's byte-identity contract.

This is not fixed in #2856 because it is a separate kernel correctness change requiring its own specification, red-first test, and fresh review.

[VikashLoomba]

The current #2856 address/undefined-sanitizer run also detects the AVX-512 arm of this alignment defect.

At PR head f544a5d5784178a843184028edf3011be62dc28f, CI tested merge ref 442bba1ff364dc34830debff33b53d78df9b9167 in job 101179830263:

src/vt/cpu/cpu_matmul_elem_avx512.cpp:121:
runtime error: load of misaligned address ...1735 for type 'const T',
which requires 2 byte alignment
#0 Bt16Avx512<(vt::cpu::ElemKind)2>

The same three cases fail: test_dots3_note_vision, test_dots3_note_audio, and test_openai_api_server_dots3_mm_forward. The other failure is the separately owned LTX2 refusal, #2853.

git log -S and blame trace this AVX-512 typed load to ea89926f58, the original wide-x86 tier commit. The complete file has identical Git blob 8f63229e279a200d18db8cb18597c2e363736f34 at the PR head and current main c796fea41f74fe90b8cf78190eeb2a5b4c977449. PR #2856 changes no CPU kernel.

The existing KERNEL-GEMM-CPU-ELEM-X86WIDE ownership covers both AVX2 and AVX-512. The repair must test odd-byte-offset BF16 through each available production tier, including the AVX-512 scalar tail, while preserving the row's byte-identity contract. This comment adds observed scope to #2908; it does not claim a fix or waive the failing job.