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wan: add dual-GPU model-parallel path for Wan 2.x LoRA training (depends on #1435)#1436

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wan: add dual-GPU model-parallel path for Wan 2.x LoRA training (depends on #1435)#1436
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genno-whittlery:dual-gpu-wan

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@genno-whittlery genno-whittlery commented May 11, 2026

Summary

Adds an env-var-gated dual-GPU model-parallel path for Wan 2.x LoRA training in examples/wanvideo/model_training/. Splits WanModel.blocks at the midpoint across cuda:0/cuda:1, with per-block forward pre-hooks bridging the cross-device activation flow.

Off by default — no behavior change unless DIFFSYNTH_DUAL_GPU=true is set.

Depends on #1435 (the patchify fix). The current main has a broken WanModel.patchify that returns the wrong shape and arity; Wan training fails immediately at the first forward call regardless of dual-GPU. Once #1435 lands, both single-GPU and dual-GPU Wan training paths work.

Depends on #1434 (the FLUX.2 dual-GPU PR) for the diffsynth/diffusion/runner.py env-gated skip of model.to(accelerator.device). Without that change, runner.py moves the manually-split DiT back to a single device and silently undoes the distribute. Both PRs use the same DIFFSYNTH_DUAL_GPU env var so one signal controls both Wan and FLUX.2 paths.

Why

The Wan 2.2 14B variants (I2V-A14B, T2V-A14B, S2V-14B, ...) are ~28 GB in bf16. The weights fit on a single 32 GB consumer card after fp8 weight-only quant, but video training activations at 480 × 832 × 49 frames with gradient checkpointing routinely push the actual step memory over 32 GB even on a 14B model. The single-GPU answer is to drop resolution / frame count / precision; the dual-GPU answer is to split the transformer blocks across two cards and let each side hold half the activations.

This patch is the same shape as the validated FLUX.2 port in #1434 from this account, adapted for Wan's simpler block structure (one DiTBlock type vs. FLUX.2's double + single split). Cross-trainer write-up at https://github.com/genno-whittlery/flux2-dual-gpu-lora.

What changed

examples/wanvideo/model_training/wan_dual_gpu_diffsynth.py (new, ~150 LOC)

The helper. Distributes:

  • cuda:0: patch_embedding, text_embedding, time_embedding, time_projection, first half of blocks, head, plus optional img_emb / ref_conv / control_adapter
  • cuda:1: second half of blocks

Registers forward_pre_hook with with_kwargs=True on every block in blocks[split_at:]WanModel.forward passes loop-level constants (context, t_mod, freqs) positionally to every iteration, so a boundary-only hook would leave subsequent cuda:1 blocks receiving the cuda:0 originals. Also one hook on head bridging activations back to cuda:0 for the final layers.

Edge case worth flagging: WanModel.freqs is a tuple of plain CPU tensors, not registered buffers, so nn.Module.to(device) doesn't move it. The helper handles this explicitly.

examples/wanvideo/model_training/train.py

  • Forces CPU model load when DIFFSYNTH_DUAL_GPU=true (so the ~28 GB bf16 transformer doesn't pre-allocate on cuda:0 before split).
  • Runs torchao.quantize_ with Float8WeightOnlyConfig + a filter_fn that excludes lora_A / lora_B Linear submodules (otherwise their requires_grad is stripped and backward fails). Same pattern from flux2: dual-GPU model-parallel + transformers 5.8 compat + Mistral-on-CPU data_process #1434.
  • Calls enable_wan_dual_gpu(model.pipe.dit) after PEFT has injected LoRA so block.to(device) carries LoRA params with their base layers.
  • After the DiT split, explicitly moves pipe.text_encoder and pipe.vae to cuda:0. The runner.py global model.to() is skipped (per flux2: dual-GPU model-parallel + transformers 5.8 compat + Mistral-on-CPU data_process #1434's gate), so non-DiT components otherwise stay on CPU and the first encode step crashes with a cross-device index_select. FLUX.2 doesn't need this because Mistral is pre-cached on CPU; Wan encodes T5 on-the-fly during the training step.

Validation

End-to-end smoke train on 2× RTX 5090 (Wan2.2-I2V-A14B high_noise_model, full bf16 base + fp8 weight-only DiT, LoRA rank 32 on q,k,v,o,ffn.0,ffn.2, 480×832×49 frames, gradient checkpointing + offload, 5 steps):

[wan-dual-gpu] pre-distribute  cuda:0 free=30.3G / 31.8G
[wan-dual-gpu] pre-distribute  cuda:1 free=30.3G / 31.8G
[wan-dual-gpu] fp8 weight-only quant done (LoRA params unmodified)
[wan-dual-gpu] moved pipe.text_encoder to cuda:0
[wan-dual-gpu] moved pipe.vae          to cuda:0
[wan-dual-gpu] post-distribute cuda:0 free=12.3G / 31.8G  (19.5G used)
[wan-dual-gpu] post-distribute cuda:1 free=23.4G / 31.8G  ( 8.4G used)

 20%|██        | 1/5 [00:45<03:03, 45.77s/it]
 40%|████      | 2/5 [01:29<02:14, 44.75s/it]
 60%|██████    | 3/5 [02:13<01:28, 44.44s/it]
 80%|████████  | 4/5 [02:58<00:44, 44.37s/it]
100%|██████████| 5/5 [03:41<00:00, 44.03s/it]
100%|██████████| 5/5 [03:41<00:00, 44.31s/it]
EXIT_CODE=0
Metric Value
Sustained s/it (steps 2-5) 44.3 s/it
Peak VRAM cuda:0 (post-distribute, pre-step) 19.5 GB / 31.84 GB
Peak VRAM cuda:1 (post-distribute, pre-step) 8.4 GB / 31.84 GB
Steps completed 5 / 5
LoRA checkpoint saved 292.59 MB (rank-32 on q,k,v,o,ffn.0,ffn.2)

Single-card fp8 baseline (--fp8_models on all four models, one 5090, no dual-GPU) for head-to-head s/it comparison is a planned follow-up — will post as a comment.

Notes for reviewers

  • @gemini-code-assist's rename feedback addressed in 8c58785: WAN_DUAL_GPU -> DIFFSYNTH_DUAL_GPU here, and coordinated FLUX2_DUAL_GPU -> DIFFSYNTH_DUAL_GPU in flux2: dual-GPU model-parallel + transformers 5.8 compat + Mistral-on-CPU data_process #1434. One env var controls dual-GPU mode for either model family. The dead os.environ["FLUX2_DUAL_GPU"]="true" re-broadcast in train.py is gone — the launcher-set env var is inherited by the same process and read by both is_dual_gpu_enabled() and the runner.py gate.
  • WanToDance support extension (gemini's other suggestion) is deferred to a follow-up PR. The current helper handles WanModel's standard blocks list; WanToDance variants have their own block list + different forward signatures that warrant a separate hooks pass to do correctly.

Test plan

  • Synthetic mini-WanModel forward + backward across cross-device split — completes, gradients propagate to both devices
  • Single-GPU path unchanged (DIFFSYNTH_DUAL_GPU unset → train.py takes existing branch)
  • Real Wan2.2-I2V-A14B end-to-end training, 2× RTX 5090, 5 steps — passes (44.3 s/it sustained, LoRA saves, ~20 G / 8 G VRAM split)
  • Single-card fp8 baseline benchmark for head-to-head s/it — 44.7 s/it vs 44.3 s/it dual-GPU, posted in comment thread
  • Cross-GPU-vendor validation (2× RTX 3090, 2× RTX 4090) — pending

Off by default -- no behavior change unless WAN_DUAL_GPU=true is set.

Wan 2.2 14B variants (I2V-A14B, T2V-A14B, S2V-14B, etc.) are ~28 GB
in bf16 -- the weights fit on one 32 GB consumer card with fp8 quant,
but video training activations at 480x832x49 frames + gradient
checkpointing routinely push the actual step over 32 GB even on a
14B model. Splitting the transformer blocks across two GPUs gives
training-step headroom that single-GPU users can't otherwise reach
without dropping resolution or frame count.

What changed:

- examples/wanvideo/model_training/wan_dual_gpu_diffsynth.py (new):
  ~150 LOC helper. Splits WanModel.blocks at the midpoint across
  cuda:0/cuda:1. Registers forward_pre_hook on every cuda:1 block
  (not just the boundary -- Wan's forward passes loop-level constants
  context / t_mod / freqs positionally to each iteration, so a
  boundary-only hook would leave subsequent blocks receiving cuda:0
  tensors). Bridges activations back to cuda:0 at the head module.
  Also explicitly moves WanModel.freqs (a tuple of plain CPU tensors,
  not registered buffers) so .to(device) doesn't miss them.

- examples/wanvideo/model_training/train.py: forces CPU model load
  when WAN_DUAL_GPU=true (so the bf16 transformer doesn't
  pre-allocate on cuda:0 before split), runs torchao
  Float8WeightOnlyConfig quantize_ with the same LoRA-skip filter
  used by the FLUX.2 port (skips lora_A/lora_B Linear submodules --
  otherwise their requires_grad is stripped and backward fails),
  then calls enable_wan_dual_gpu(model.pipe.dit) after PEFT has
  injected LoRA so block.to(device) carries LoRA params with their
  base layers. Also sets FLUX2_DUAL_GPU=true after distribute so the
  existing runner.py branch from PR modelscope#1434 catches the
  device_placement=[False, ...] case in accelerator.prepare without
  needing a parallel WAN_DUAL_GPU branch there.

Depends on modelscope#1435 (patchify fix). The current main has a broken
WanModel.patchify that returns the wrong shape and arity; Wan
training fails immediately at the first forward call regardless of
dual-GPU. Once modelscope#1435 lands, both single-GPU and dual-GPU Wan training
paths work.

Validated locally on 2x RTX 5090 with a synthetic 8-layer WanModel
(same architecture shape as real Wan 2.2, miniaturized to fit a
quick smoke test): forward + backward complete across the cross-
device split, output round-trips to the original (B, C, T, H, W)
shape, LoRA gradients land on both cuda:0 and cuda:1 (proving cross-
device autograd).

Same patch shape as the validated FLUX.2 port in PR modelscope#1434 from this
account. Both share the runner.py model-parallel branch.
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Code Review

This pull request implements dual-GPU model parallelism for Wan video DiT training, allowing the 14B model to be trained on consumer GPUs by splitting it across two devices. It introduces a new helper module for device distribution and updates the training script to perform CPU-side FP8 quantization before moving model blocks. Reviewers suggested extending the device placement logic and activation hooks to support additional Wan variants like WanToDance. Additionally, it was recommended to use a more generic environment variable name instead of FLUX2_DUAL_GPU to signal dual-GPU mode in the training runner.

Comment on lines +112 to +117
if hasattr(dit, "img_emb") and dit.img_emb is not None:
dit.img_emb.to(cuda0)
if hasattr(dit, "ref_conv") and dit.ref_conv is not None:
dit.ref_conv.to(cuda0)
if hasattr(dit, "control_adapter") and dit.control_adapter is not None:
dit.control_adapter.to(cuda0)
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high

Several optional modules used in specific Wan variants (such as WanToDance) are not being moved to cuda:0. This will lead to device mismatch errors during training if these variants are used in dual-GPU mode.

Suggested change
if hasattr(dit, "img_emb") and dit.img_emb is not None:
dit.img_emb.to(cuda0)
if hasattr(dit, "ref_conv") and dit.ref_conv is not None:
dit.ref_conv.to(cuda0)
if hasattr(dit, "control_adapter") and dit.control_adapter is not None:
dit.control_adapter.to(cuda0)
if hasattr(dit, "img_emb") and dit.img_emb is not None:
dit.img_emb.to(cuda0)
if hasattr(dit, "ref_conv") and dit.ref_conv is not None:
dit.ref_conv.to(cuda0)
if hasattr(dit, "control_adapter") and dit.control_adapter is not None:
dit.control_adapter.to(cuda0)
# Move WanToDance specific modules
for attr in ["img_emb_refimage", "img_emb_refface", "music_projection", "music_encoder", "patch_embedding_global", "head_global"]:
if hasattr(dit, attr) and getattr(dit, attr) is not None:
getattr(dit, attr).to(cuda0)

Comment on lines +138 to +140
dit.head.register_forward_pre_hook(
_make_device_bridge_hook(cuda0), with_kwargs=True
)
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high

The activation bridge hook is only registered on dit.head. However, some Wan variants (like WanToDance) use dit.head_global instead. If head_global is used, the activations coming from the last block on cuda:1 will not be moved back to cuda:0, causing a device mismatch error.

Suggested change
dit.head.register_forward_pre_hook(
_make_device_bridge_hook(cuda0), with_kwargs=True
)
# Bridge activations back to cuda:0 for the head + unpatchify.
for head_attr in ["head", "head_global"]:
if hasattr(dit, head_attr) and getattr(dit, head_attr) is not None:
getattr(dit, head_attr).register_forward_pre_hook(
_make_device_bridge_hook(cuda0), with_kwargs=True
)

# Signal launch_training_task to skip its own model.to() move
# (runner.py keys off FLUX2_DUAL_GPU for that branch; reuse to
# avoid duplicating the device-placement logic).
os.environ["FLUX2_DUAL_GPU"] = "true"
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medium

Setting the FLUX2_DUAL_GPU environment variable to control behavior for a Wan model is confusing and creates a hidden, model-specific dependency in the training runner. It would be better to use a more generic environment variable name, such as DIFFSYNTH_DUAL_GPU, and update the logic in runner.py to recognize this shared flag for any model-parallel training path.

@genno-whittlery genno-whittlery marked this pull request as draft May 11, 2026 14:41
Per @gemini-code-assist review on modelscope#1436: use a model-neutral env var
name. This change:

- WAN_DUAL_GPU            -> DIFFSYNTH_DUAL_GPU
- WAN_DUAL_GPU_SPLIT_AT   -> DIFFSYNTH_DUAL_GPU_SPLIT_AT

The same generic name will be adopted in modelscope#1434 (flux2 dual-GPU) so a
single env var controls dual-GPU mode for both Wan and FLUX.2 paths.
Helper function name (is_dual_gpu_enabled) and helper module file
name (wan_dual_gpu_diffsynth.py) kept Wan-specific to make the
import call sites at the entry-point clearer.

Also dropped the now-redundant os.environ["FLUX2_DUAL_GPU"]="true"
re-broadcast in train.py — the launcher-set DIFFSYNTH_DUAL_GPU is
inherited by the same process and read by both is_dual_gpu_enabled()
and runner.py's gate (after modelscope#1434 lands its matching rename).
Added a comment block making the implicit runtime dependency on
modelscope#1434's runner.py change explicit.
genno-whittlery added a commit to genno-whittlery/DiffSynth-Studio that referenced this pull request May 11, 2026
Per @gemini-code-assist review on modelscope#1436: model-neutral env var name so
a single signal controls dual-GPU mode for both FLUX.2 and Wan paths.
This change:

- FLUX2_DUAL_GPU            -> DIFFSYNTH_DUAL_GPU
- FLUX2_DUAL_GPU_SPLIT_AT   -> DIFFSYNTH_DUAL_GPU_SPLIT_AT

Function names (enable_flux2_dual_gpu) and the helper module name
(flux2_dual_gpu_diffsynth.py) keep the model-specific naming since
they're the entry points users explicitly import for FLUX.2 training.

Coordinated with PR modelscope#1436 which adopts the same DIFFSYNTH_DUAL_GPU
gate on the Wan side. Once both merge, one env var enables dual-GPU
for either model family; runner.py recognizes the gate regardless of
which family the training script targets.
@genno-whittlery genno-whittlery marked this pull request as ready for review May 11, 2026 17:38
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Out of draft — both review gates passed:

  1. @gemini-code-assist rename: FLUX2_DUAL_GPU and WAN_DUAL_GPU collapsed to a single model-neutral DIFFSYNTH_DUAL_GPU env var. Coordinated commit on the FLUX.2 PR (flux2: dual-GPU model-parallel + transformers 5.8 compat + Mistral-on-CPU data_process #1434) renames the matching gate in runner.py. Detail in the PR body's "Notes for reviewers" section.

  2. On-device validation: real Wan 2.2-I2V-A14B (high_noise_model) on 2× RTX 5090, full bf16 base + fp8 weight-only DiT, 5-step smoke train at 480×832×49 frames passes at 44.3 s/it sustained with VRAM at 19.5 G / 8.4 G across the two cards; LoRA checkpoint saves cleanly. Full numbers + log excerpt in the PR body.

The WanToDance extension suggestion is parked as a follow-up — kept this PR focused on the standard WanModel.blocks distribute since WanToDance variants have a different block layout and forward signature that warrant a separate pass.

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Thank you for the update and for coordinating the environment variable naming across the FLUX.2 and Wan model families. The validation results on the 2× RTX 5090 setup look excellent, and it's great to see the dual-GPU model-parallel path successfully handling the memory requirements for the 14B variants. I have no further comments on this implementation. Good luck with the remaining cross-GPU-vendor validation.

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Single-card fp8 baseline — head-to-head with dual-GPU bf16

Ran the upstream special/fp8_training/ style recipe on one RTX 5090 for direct s/it comparison. Same model (Wan2.2-I2V-A14B high_noise), same dataset, same LoRA rank/target, same 480×832×49 resolution, same --use_gradient_checkpointing[_offload]. Only delta: DIFFSYNTH_DUAL_GPU unset, CUDA_VISIBLE_DEVICES=0, --fp8_models applied to DiT + T5 + VAE (vs dual-GPU's bf16 T5/VAE + fp8 DiT only).

Config Sustained s/it (steps 2-5) Total 5 steps Step 1 (warm-up) Peak VRAM LoRA saved
Dual-GPU bf16 (this PR) 44.31 s/it 3:41 45.77s cuda:0 19.5G + cuda:1 8.4G 292.59 MB
Single-card fp8 44.73 s/it 3:43 45.12s cuda:0 ~22-25G (estimated) 292.59 MB
Δ +0.4 s/it (0.9%) +2s -0.65s identical

Takeaway: at this resolution / frame count, the dual-GPU bf16 path is not measurably faster than the supported single-card fp8 recipe. Cross-device hooks add per-block bridging overhead that approximately cancels the speedup from fp8 weights being routed through the slower fp8 GEMM path on Blackwell.

Where dual-GPU actually wins:

  1. No precision loss on DiT or text encoder. Single-card fp8 quantizes T5 — long-prompt encode fidelity degrades visibly on cat-face fine detail in our IP-character training (separate validation). Dual-GPU keeps T5 bf16.
  2. Headroom for resolution / frame increases. Single-card fp8 is already at ~22-25 GB / 32 GB; bumping to 720×1280 or 81 frames pushes over even with offload. Dual-GPU has cuda:1 sitting at 8.4 GB — plenty of room to take more of the activation load.
  3. No --use_gradient_checkpointing_offload needed in principle. Both runs here used it for safety, but the dual-GPU split has headroom to disable CPU offload and reclaim the host↔device transfer cost (rough estimate: 30-40% s/it improvement once we tune). Will benchmark in a follow-up.

So the framing isn't "dual-GPU is faster" — it's "dual-GPU lets you train Wan 2.2 A14B in full bf16 precision on a pair of 32 GB cards, where the single-card path requires fp8 weights everywhere." For users training characters / fine-detail subjects, that precision matters; for users who just want a working LoRA in any precision, the single-card recipe in special/fp8_training/ is great and this PR is a no-op.

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Adding context: the 24 GB market is the real motivation.

The 32 GB / 32 GB benchmark above understates the value because the single-card fp8 path actually fits on a single 5090. On the bulk of the consumer-GPU population (24 GB cards: RTX 3090, RTX 4090, RTX A5000) the story is very different:

GPU class Single-card fp8 Dual-GPU bf16 (this PR)
1× 32 GB (5090) Fits (~22-25 GB peak) — 44.7 s/it ✅ Not needed for fitting; gives precision + headroom
1× 24 GB (3090/4090) OOM at default config; needs --offload_models + smaller resolution + fp8 everywhere to fit at all 2× 24 GB: cuda:0 ~22 GB + cuda:1 ~7 GB — fits at full bf16, no offload_models rotation
1× 16 GB (4080) Won't fit even with aggressive offload 2× 16 GB: would need split + fp8 on both halves; not validated yet but architecturally fine

In other words: this isn't really about being faster than the single-card fp8 recipe — it's about enabling Wan 2.2 14B training in clean bf16 on hardware that otherwise can't run it at all, or only with the heaviest of the special/low_vram_training/ tricks (gradient_checkpointing_offload + offload_models rotation + dataset_repeat caching across two stages). Most users have 24 GB cards, not 32 GB ones.

We don't have a 2× 24 GB rig on the bench right now to post measured numbers, but the architecture (~7 GB DiT half on each + bf16 T5 on cuda:0) leaves comfortable headroom on 24 GB. Happy to validate on 2× 3090/4090 if a maintainer has access and wants concrete numbers before merge.

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