Highlights
- Pro
Pinned Loading
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Hybrid-Transfer-Learning-for-2D-Materials-Carrier-Mobility
Hybrid-Transfer-Learning-for-2D-Materials-Carrier-Mobility Publicupdated model with 2d sic prediction
Python 1
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RISC-V-FPGA-Processors
RISC-V-FPGA-Processors PublicAI-powered RISC-V processor designs in Verilog and VHDL — from 16-bit to 64-bit with IEEE 754 FPU, targeting Basys 3 (XC7A35T)
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