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Pull requests: diffblue/hw-cbmc

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Pull requests list

verilog: add missing statements to collect_symbols and interface_module_item
#1943 opened Jun 28, 2026 by kroening Collaborator Loading…
2 tasks
Add vlsim: Verilog simulator using the src/verilog front-end
#1942 opened Jun 28, 2026 by kroening Collaborator Loading…
5 tasks
Verilog: support `pragma preprocessor directive
#1941 opened Jun 28, 2026 by kroening Collaborator Loading…
Verilog: support for `undefineall
#1940 opened Jun 28, 2026 by kroening Collaborator Loading…
BTOR2: implement sdivo and udivo overflow operators
#1939 opened Jun 27, 2026 by kroening Collaborator Loading…
3 tasks
BTOR2: validate that 'next' first argument is a state variable
#1938 opened Jun 27, 2026 by kroening Collaborator Loading…
2 tasks
BTOR2: validate operand count for all operators
#1937 opened Jun 27, 2026 by kroening Collaborator Loading…
2 tasks
BTOR2: reject duplicate sort and node IDs
#1936 opened Jun 27, 2026 by kroening Collaborator Loading…
3 tasks
AIGER: KNOWNBUG tests for front-end bugs found by fuzzing
#1935 opened Jun 27, 2026 by kroening Collaborator Loading…
BTOR2: validate operand types and slice bounds
#1934 opened Jun 27, 2026 by kroening Collaborator Loading…
AIGER output
#1928 opened Jun 21, 2026 by kroening Collaborator • Draft
fastppa: word-level delay, area, and power estimation tool
#1927 opened Jun 21, 2026 by kroening Collaborator • Draft
1
Verilog: split synthesis into behavioral and structural cleanup Verilog
#1926 opened Jun 21, 2026 by kroening Collaborator • Draft
Verilog: support for let expressions with ports
#1925 opened Jun 21, 2026 by kroening Collaborator • Draft
SystemVerilog: named sequence/property ports Verilog
#1923 opened Jun 21, 2026 by kroening Collaborator • Draft
Verilog: preresolving identifiers Verilog
#1921 opened Jun 20, 2026 by kroening Collaborator • Draft
introduce verilog_let_typet Verilog
#1919 opened Jun 20, 2026 by kroening Collaborator • Draft
Verilog: derive identifier from annotated scope cleanup Verilog
#1912 opened Jun 19, 2026 by kroening Collaborator • Draft
verilog_identifier_exprt now has structured scope stack Verilog
#1910 opened Jun 19, 2026 by kroening Collaborator • Draft
Verilog: SystemVerilog interfaces
#1907 opened Jun 18, 2026 by kroening Collaborator • Draft
9 tasks done
Verilog: fix unsigned/signed parameter without explicit range Verilog
#1902 opened Jun 16, 2026 by kroening Collaborator • Draft
Verilog: $root module does not need ports cleanup Verilog
#1875 opened Jun 4, 2026 by kroening Collaborator • Draft
module types now contain the symbol set Verilog
#1869 opened May 24, 2026 by kroening Collaborator • Draft
annotate enum types with their identifier cleanup Verilog
#1863 opened May 22, 2026 by kroening Collaborator • Draft
use existing verilog_ebmc_languaget::typecheck_module for $root cleanup Verilog
#1855 opened May 17, 2026 by kroening Collaborator • Draft
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