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MultiClockSpec chiselTest fails with recent Verilator version

Status: Open.

#5418 In chipsalliance/chisel;

· maartenboersma opened on Jun 16, 2026

[firrtl] Hardware with nested direction generates failing firrtl with Reg / RegNext

Status: Open.

#5411 In chipsalliance/chisel;

· Hamster5295 opened on Jun 14, 2026

Better error message for misuse of Domain association to ports

Status: Open.

#5407 In chipsalliance/chisel;

· uenoku opened on Jun 9, 2026

ModuleChoice does not connect implicit clock/reset to FixedIOModule targets

Status: Open.

#5383 In chipsalliance/chisel;

· uenoku opened on May 27, 2026

"-disable-all-randomization" can't work when the module with RequireAsyncReset

Status: Open.

#5357 In chipsalliance/chisel;

· qiaomufenlin opened on May 18, 2026

[ChiselSim] Flag --trace-threads is deprecated since Verilator v5.048

Status: Open.

#5335 In chipsalliance/chisel;

· Hamster5295 opened on May 14, 2026

[doc] Add documentation about layer-under-layer errors and how to mitigate

Status: Open.

#5244 In chipsalliance/chisel;

· seldridge opened on Mar 25, 2026

SRAM.masked broken when the mask is a constant of all 1s

Status: Open.

#5243 In chipsalliance/chisel;

· elipsitz opened on Mar 24, 2026

suffix always be "sv"

Status: Open.

#5231 In chipsalliance/chisel;

· balanx opened on Mar 14, 2026

ChiselSim cannot deal with 0-width signals and DontCare values

Status: Open.

#5230 In chipsalliance/chisel;

· ccromjongh opened on Mar 13, 2026

Escape FIRRTL Keywords in Emission

Status: Open.

#5218 In chipsalliance/chisel;

· seldridge opened on Feb 27, 2026

Boring from a Probe with U-turn can cause illegal FIRRTL

bug

Status: Open.

#5130 In chipsalliance/chisel;

· seldridge opened on Dec 20, 2025