riscv: trap reserved C.LUI/C.ADDI16SP encodings instead of mis-decoding them - #286
Merged
Merged
Conversation
Owner
|
How come is |
Owner
|
Other than that, the fix is sound. Previously both cases fell through into |
…ng them
riscv_emulate_c_c1() falls through from the reserved c.lui/c.addi16sp
code points (nzimm == 0, not a valid c.mop.N) into the c.misc-alu
decoder, executing reserved encodings as c.srli/c.srai/c.andi/c.sub
instructions. The RV64 c.addiw rd == x0 code points are also reserved
per the spec ("valid only when rd != x0") and were falling through the
same way.
Both paths now return explicitly: the c.lui/c.addi16sp reserved slot
raises an illegal-instruction trap, and c.addiw rd == x0 raises an
illegal-instruction trap instead of being executed or treated as a
HINT.
carlosqwqqwq
force-pushed
the
fix/c-lui-reserved-trap
branch
from
August 13, 2026 01:53
b11a8aa to
47c19fe
Compare
Author
|
You are right - thank you for the catch. I checked the spec: C.ADDIW is valid only when rd != x0; the rd == x0 code points are reserved (not HINTs), and QEMU decodes them as c64_illegal. I have updated the patch so c.addiw rd == x0 now raises an illegal-instruction trap instead of being treated as a no-op, and force-pushed. The c.lui/c.addi16sp nzimm == 0 slot (the main subject of the PR) is unchanged. |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Fix: trap reserved C.LUI/C.ADDI16SP and C.ADDIW rd=x0 encodings
Problem
riscv_emulate_c_c1()insrc/cpu/riscv_compressed.hfalls through from thereserved
c.lui/c.addi16sp/c.mopcode points into thec.misc-aludecoder, executing reserved encodings as
c.srli/c.srai/c.andi/c.sub-family instructions. The RV64
c.addiwrd == x0code points are alsoreserved per the spec ("valid only when rd != x0") and fell through the same
way.
Change
Both affected paths now return explicitly instead of falling through:
case 0x01(RV64):c.addiwwithrd == x0(reserved) ->riscv_illegal_insn()case 0x03:c.lui/c.addi16spwithnzimm == 0that is not a validc.mop.N->
riscv_illegal_insn()Verification
c.lui-slot encodings: trap on native RISC-V hardware (SIGILL), QEMU(SIGILL), and now RVVM (both JIT and interpreter).
c.addiw x0, immreserved encodings: now raise an illegal-instructiontrap, matching the spec and QEMU (
c64_illegal).c.lui x0, 1hint,c.mop.N(Zcmop),c.addiwwithrd != 0,and all other C1 encodings still execute correctly.
Fixes #284.