riscv: include negative minimum values in FCVT fit checks

[carlosqwqqwq]

riscv: include negative minimum values in FCVT fit checks

Fixes #277

Commit message

riscv: include negative minimum values in FCVT fit checks

Description

The float-to-integer fit predicates use a strict magnitude comparison and classify exactly representable -2^31/-2^63 inputs as invalid. Include the negative minimum bit patterns while retaining the positive overflow checks. The change is limited to the four fit predicates in src/util/fpu_lib.h. It does not include the probe or research logs in the upstream change.

Validation

• The witness runs on native RISC-V hardware and QEMU and on the affected RVVM build; the isolated patched build matches both references.
• Both the interpreter and JIT lanes were exercised, and the patched build is limited to this root.

[purplesyringa]

You can speed up this check with something like

return (bit_rotl32(f, 1) ^ 1) <= 0x9E000000U;

Technically you can remove yet another instruction on x86 by going

shl f, 1
sbc f, 0x9E000000
jb ...

but it's messy in C, can't be implemented efficiently on ARM, and is deoptimized by GCC, so the rotl approach is probably the best.

_Bool fpu_f32_fits_i32_yuki(unsigned f) {
    unsigned twof;
    _Bool carry_in = __builtin_add_overflow(f, f, &twof);
    unsigned carry_out;
    __builtin_subc(twof, 0x9E000000U, carry_in, &carry_out);
    return carry_out;
}

[carlosqwqqwq]

Thanks for the suggestion! Adopted the rotate-based check in all four fits helpers: (bit_rotl32(u, 1) ^ 1) <= 0x9E000000U for f32/i32, and the rotl64 counterparts for f64/i32 and the i64 pairs. Verified bit-exact equivalence against the previous two-comparison form over the full exponent/mantissa grids (zero mismatches), rebuilt cleanly, and force-pushed.