riscv: enforce the fixed rs2 field for LR.W and LR.D

[carlosqwqqwq]

riscv: enforce the fixed rs2 field for LR.W and LR.D

Fixes #266

Commit message

riscv: enforce the fixed rs2 field for LR.W and LR.D

Description

The RISC-V LR.W and LR.D encodings require rs2=x0. RVVM currently dispatches non-zero rs2 encodings as valid load-reserved operations. Reject those reserved encodings before the alignment and reservation path while preserving legal LR controls.

Validation

• Invalid D/W encodings and legal controls were run on native RV64, QEMU, interpreter, JIT, fixed interpreter, and fixed JIT paths.
• The proposed change is limited to the two atomic LR helpers.
• The result matrix for each lane is attached with the witness outputs.