GitHub - Jerry-Terrasse/RISCU: My implementation of a single cycle CPU based on RISC-V ISA

RISCU

RISCU: RISC-V Single Cycle CPU

My implementation of a single cycle CPU based on RISC-V ISA, also my lab2 of Computer Organization course.

data path

Name		Name	Last commit message	Last commit date
Latest commit History 55 Commits
.Xil		.Xil
assets		assets
proj_single_cycle.hw/hw_1		proj_single_cycle.hw/hw_1
proj_single_cycle.sim/sim_1/behav/xsim		proj_single_cycle.sim/sim_1/behav/xsim
proj_single_cycle.srcs		proj_single_cycle.srcs
.gitignore		.gitignore
CPU.circ		CPU.circ
README.md		README.md
calculator.coe		calculator.coe
controller.bin		controller.bin
controller.coe		controller.coe
controller.csv		controller.csv
data_ram.coe		data_ram.coe
data_ram_0.coe		data_ram_0.coe
data_ram_1.coe		data_ram_1.coe
data_ram_2.coe		data_ram_2.coe
data_ram_3.coe		data_ram_3.coe
gen_controller_coe.py		gen_controller_coe.py
inst_rom.coe		inst_rom.coe
proj_single_cycle.xpr		proj_single_cycle.xpr
summary.md		summary.md
vivado.jou		vivado.jou
vivado_11592.backup.jou		vivado_11592.backup.jou
vivado_11940.backup.jou		vivado_11940.backup.jou
vivado_15812.backup.jou		vivado_15812.backup.jou
vivado_16608.backup.jou		vivado_16608.backup.jou
vivado_2484.backup.jou		vivado_2484.backup.jou
waveform_analysis.md		waveform_analysis.md