ad-astra

Ad Astra

These SystemVerilog examples use starfields and hardware sprites to build up a simple greetings demo. The final demo is in file top_greet.sv.

I created Ad Astra in 2018; it was my first FPGA demo, but I didn't release it at a party (for one thing it has no music). This version remains similar to the original source, but has some minor updates to work with the Project F Verilog library.

This demo has an associated Project F blog post: Ad Astra.
New to FPGA graphics design? Check out Beginning FPGA Graphics.

NB. The included fonts are distributed under different licences: see the individual font files for details.

Included demos:

• top_lfsr - simple background using a linear feedback register (LFSR)
• top_starfield - layered starfields using multiple LFSRs
• top_space_f - 'F' character overlaid on starfield using sprite
• top_hello_en - multiple sprites spell "Hello" on starfield
• top_hello_jp - multiple sprites spell "こんにちは" on starfield
• top_greet_v1 - greetings to open source hardware projects
• top_greet - greetings to open source hardware projects with copper colours

Greetings generated by an Artix-7 FPGA.

Arty Build

To create a Vivado project for the Digilent Arty (original or A7-35T); clone the projf-explore git repo, then start Vivado and run the following in the Tcl console:

cd projf-explore/demos/ad-astra/xc7/vivado
source ./create_project.tcl

You can then build top_greet, top_hello_jp etc. as you would for any Vivado project.