[hw] Split DV and DD for lowRISC vendored IPs

This would allow us to pull in the upstream DV files while maintmaining
the DD files in the same state as before. This is needed as some RTL
changes are not desired while we need to get latest DV changes from
upstream. This will work until the DV diverge from the DD. Then, another
solution will be needed to keep the DV and DD in sync (maybe cherry-
picking individual changes in an OpenTitan fork dedicated to Mocha which
will be manually maintained for Mocha needs).

Signed-off-by: martin-velay <mvelay@lowrisc.org>

Author: martin-velay

hw/vendor/lowrisc_ip.vendor.hjson

@@ -34,7 +34,7 @@
     {from: "hw/ip/lc_ctrl",      to: "ip/lc_ctrl"}, // Dependency of crossbar and power manager.
     {from: "hw/ip/rom_ctrl",     to: "ip/rom_ctrl", patch_dir: "rom_ctrl"}, // Read-only memory.
     {from: "hw/ip/rv_core_ibex", to: "ip/rv_core_pkg", patch_dir: "rv_core_pkg"}, // RISC-V core package.
-    {from: "hw/ip/rv_timer",     to: "ip/rv_timer", patch_dir: "rv_timer"}, // Timer.
+    {from: "hw/ip/rv_timer",     to: "ip/rv_timer"}, // Timer.
     {from: "hw/ip/spi_device",   to: "ip/spi_device", patch_dir: "spi_device"}, // SPI device.
     {from: "hw/ip/spi_host",     to: "ip/spi_host", patch_dir: "spi_host"}, // SPI host.
     {from: "hw/ip/tlul",         to: "ip/tlul", patch_dir: "tlul"}, // Memory bus.
@@ -55,21 +55,11 @@
 
     // Lint.
     {from: "hw/lint", to: "lint", patch_dir: "lint"},
-
-    // Simulation.
-    {from: "hw/dv/dpi/gpiodpi", to: "dv/dpi/gpiodpi", patch_dir: "gpiodpi"},
-    {from: "hw/dv/dpi/spidpi",  to: "dv/dpi/spidpi"},
-    {from: "hw/dv/dpi/uartdpi", to: "dv/dpi/uartdpi"},
-    {from: "hw/dv/sv",          to: "dv/sv", patch_dir: "dv_sv"},
-    {from: "hw/dv/verilator",   to: "dv/verilator", patch_dir: "dv_verilator"},
-
-    // Verification.
-    {from: "hw/dv/tools",       to: "dv/tools",     patch_dir: "dv_tools"},
-    {from: "hw/formal/tools",   to: "formal/tools", patch_dir: "formal_tools"},
   ],
 
   exclude_from_upstream: [
-    "*/BUILD",
-    "hw/dv/tools/vcs",
+    "**/BUILD",
+    "hw/ip/*/dv",
+    "hw/ip_templates/*/dv",
   ],
 }

hw/vendor/lowrisc_ip_dv.lock.hjson

@@ -0,0 +1,14 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// This file is generated by the util/vendor script. Please do not modify it
+// manually.
+
+{
+  upstream:
+  {
+    url: https://github.com/lowRISC/opentitan
+    rev: bf4a2b24e41742151cfce9c4041e959a3ba76ca3
+  }
+}

hw/vendor/lowrisc_ip_dv.vendor.hjson

@@ -0,0 +1,49 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  name: "lowrisc_ip_dv",
+  target_dir: "lowrisc_ip",
+  patch_dir: "patches/lowrisc_ip",
+
+  upstream: {
+    url: "https://github.com/lowRISC/opentitan"
+    // Pinned revision of main branch
+    rev: "master"
+  }
+
+  mapping: [
+    // Shared DV infrastructure.
+    {from: "hw/dv/dpi/gpiodpi", to: "dv/dpi/gpiodpi", patch_dir: "gpiodpi"},
+    {from: "hw/dv/dpi/spidpi",  to: "dv/dpi/spidpi"},
+    {from: "hw/dv/dpi/uartdpi", to: "dv/dpi/uartdpi"},
+    {from: "hw/dv/sv",          to: "dv/sv", patch_dir: "dv_sv"},
+    {from: "hw/dv/verilator",   to: "dv/verilator", patch_dir: "dv_verilator"},
+    {from: "hw/dv/tools",       to: "dv/tools",     patch_dir: "dv_tools"},
+    {from: "hw/formal/tools",   to: "formal/tools", patch_dir: "formal_tools"},
+
+    // Per-IP DV environments.
+    {from: "hw/ip/entropy_src/dv", to: "ip/entropy_src/dv", patch_dir: "entropy_src_dv"},
+    {from: "hw/ip/i2c/dv",        to: "ip/i2c/dv",        patch_dir: "i2c_dv"},
+    {from: "hw/ip/kmac/dv",       to: "ip/kmac/dv"},
+    {from: "hw/ip/lc_ctrl/dv",    to: "ip/lc_ctrl/dv"},
+    {from: "hw/ip/prim/dv",       to: "ip/prim/dv",        patch_dir: "prim_dv"},
+    {from: "hw/ip/rom_ctrl/dv",   to: "ip/rom_ctrl/dv",   patch_dir: "rom_ctrl_dv"},
+    {from: "hw/ip/rv_timer/dv",   to: "ip/rv_timer/dv",   patch_dir: "rv_timer_dv"},
+    {from: "hw/ip/spi_device/dv", to: "ip/spi_device/dv", patch_dir: "spi_device_dv"},
+    {from: "hw/ip/spi_host/dv",   to: "ip/spi_host/dv",   patch_dir: "spi_host_dv"},
+    {from: "hw/ip/uart/dv",       to: "ip/uart/dv",        patch_dir: "uart_dv"},
+
+    // Per-IP-template DV environments.
+    {from: "hw/ip_templates/alert_handler/dv", to: "ip_templates/alert_handler/dv"},
+    {from: "hw/ip_templates/clkmgr/dv",        to: "ip_templates/clkmgr/dv"},
+    {from: "hw/ip_templates/gpio/dv",          to: "ip_templates/gpio/dv",   patch_dir: "gpio_dv"},
+    {from: "hw/ip_templates/pwrmgr/dv",        to: "ip_templates/pwrmgr/dv", patch_dir: "pwrmgr_dv"},
+    {from: "hw/ip_templates/rstmgr/dv",        to: "ip_templates/rstmgr/dv", patch_dir: "rstmgr_dv"},
+  ],
+
+  exclude_from_upstream: [
+    "**/BUILD",
+    "hw/dv/tools/vcs",
+  ],
+}

hw/vendor/patches/lowrisc_ip/entropy_src/0002_Fix_Testplan_Paths.patch

@@ -0,0 +1,21 @@
+diff --git a/data/entropy_src_testplan.hjson b/data/entropy_src_testplan.hjson
+index 4d296d9..29a4c0c 100644
+--- a/data/entropy_src_testplan.hjson
++++ b/data/entropy_src_testplan.hjson
+@@ -3,11 +3,11 @@
+ // SPDX-License-Identifier: Apache-2.0
+ {
+   name: "entropy_src"
+-  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
+-                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+-                     "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
+-                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
+-                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
++  import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
++                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
++                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
++                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
++                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
+                      "entropy_src_sec_cm_testplan.hjson"]
+   testpoints: [
+     {

…c_ip/entropy_src/0002_Fix_DV_Paths.patch …p/entropy_src_dv/0001_Fix_DV_Paths.patchhw/vendor/patches/lowrisc_ip/entropy_src/0002_Fix_DV_Paths.patch renamed to hw/vendor/patches/lowrisc_ip/entropy_src_dv/0001_Fix_DV_Paths.patch hw/vendor/patches/lowrisc_ip/entropy_src/0002_Fix_DV_Paths.patch renamed to hw/vendor/patches/lowrisc_ip/entropy_src_dv/0001_Fix_DV_Paths.patch

@@ -1,39 +1,18 @@
-diff --git a/data/entropy_src_testplan.hjson b/data/entropy_src_testplan.hjson
-index 4d296d9..29a4c0c 100644
---- a/data/entropy_src_testplan.hjson
-+++ b/data/entropy_src_testplan.hjson
-@@ -3,11 +3,11 @@
- // SPDX-License-Identifier: Apache-2.0
- {
-   name: "entropy_src"
--  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
--                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
--                     "hw/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
--                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
--                     "hw/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
-+  import_testplans: ["hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/csr_testplan.hjson",
-+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
-+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/alert_test_testplan.hjson",
-+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson",
-+                     "hw/vendor/lowrisc_ip/dv/tools/dvsim/testplans/stress_all_with_reset_testplan.hjson",
-                      "entropy_src_sec_cm_testplan.hjson"]
-   testpoints: [
-     {
-diff --git a/dv/entropy_src_base_sim_cfg.hjson b/dv/entropy_src_base_sim_cfg.hjson
+diff --git a/entropy_src_base_sim_cfg.hjson b/entropy_src_base_sim_cfg.hjson
 index 3a79a86..df6660a 100644
---- a/dv/entropy_src_base_sim_cfg.hjson
-+++ b/dv/entropy_src_base_sim_cfg.hjson
+--- a/entropy_src_base_sim_cfg.hjson
++++ b/entropy_src_base_sim_cfg.hjson
 @@ -18,22 +18,22 @@
    fusesoc_core: lowrisc:dv:entropy_src_sim:0.1
- 
+
    // Testplan hjson file.
 -  testplan: "{proj_root}/hw/ip/entropy_src/data/entropy_src_testplan.hjson"
 +  testplan: "{proj_root}/hw/vendor/lowrisc_ip/ip/entropy_src/data/entropy_src_testplan.hjson"
- 
+
    // RAL spec - used to generate the RAL model.
 -  ral_spec: "{proj_root}/hw/ip/entropy_src/data/entropy_src.hjson"
 +  ral_spec: "{proj_root}/hw/vendor/lowrisc_ip/ip/entropy_src/data/entropy_src.hjson"
- 
+
    // Import additional common sim cfg files.
    import_cfgs: [// Project wide common sim cfg file
 -                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
@@ -52,11 +31,11 @@ index 3a79a86..df6660a 100644
                  // TODO: import `stress_tests.hjson` once hanging issue is resolved.
 -                "{proj_root}/hw/dv/tools/dvsim/tests/stress_all_test.hjson"]
 +                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_all_test.hjson"]
- 
+
    // Add additional tops for simulation.
    sim_tops: ["entropy_src_bind", "entropy_src_cov_bind", "sec_cm_prim_onehot_check_bind"]
 @@ -43,18 +43,18 @@
- 
+
    xcelium_cov_refine_files: [
    // TODO(#16276): Finalize coverage on ExtHT ports & remove the following exclusion file
 -  "{proj_root}/hw/ip/entropy_src/dv/cov/entropy_src_extht_exclusions.vRefine"
@@ -78,31 +57,31 @@ index 3a79a86..df6660a 100644
 -  "{proj_root}/hw/ip/entropy_src/dv/cov/entropy_src_fifo_in_excl.vRefine",
 +  "{proj_root}/hw/vendor/lowrisc_ip/ip/entropy_src/dv/cov/entropy_src_fifo_in_excl.vRefine",
    ]
- 
+
    // Default UVM test and seq class name.
-diff --git a/dv/entropy_src_rng16bits_sim_cfg.hjson b/dv/entropy_src_rng16bits_sim_cfg.hjson
+diff --git a/entropy_src_rng16bits_sim_cfg.hjson b/entropy_src_rng16bits_sim_cfg.hjson
 index 0c2743b..bb36ab4 100644
---- a/dv/entropy_src_rng16bits_sim_cfg.hjson
-+++ b/dv/entropy_src_rng16bits_sim_cfg.hjson
+--- a/entropy_src_rng16bits_sim_cfg.hjson
++++ b/entropy_src_rng16bits_sim_cfg.hjson
 @@ -7,7 +7,7 @@
    variant: rng_16bits
- 
+
    // Import the base entropy_src sim_cfg file
 -  import_cfgs: ["{proj_root}/hw/ip/entropy_src/dv/entropy_src_base_sim_cfg.hjson"]
 +  import_cfgs: ["{proj_root}/hw/vendor/lowrisc_ip/ip/entropy_src/dv/entropy_src_base_sim_cfg.hjson"]
- 
+
    build_opts: ["+define+RNG_BUS_WIDTH=16",
                 "+define+RNG_BUS_BIT_SEL_WIDTH=4",
-diff --git a/dv/entropy_src_rng4bits_sim_cfg.hjson b/dv/entropy_src_rng4bits_sim_cfg.hjson
+diff --git a/entropy_src_rng4bits_sim_cfg.hjson b/entropy_src_rng4bits_sim_cfg.hjson
 index cc7ccb7..d0a21ca 100644
---- a/dv/entropy_src_rng4bits_sim_cfg.hjson
-+++ b/dv/entropy_src_rng4bits_sim_cfg.hjson
+--- a/entropy_src_rng4bits_sim_cfg.hjson
++++ b/entropy_src_rng4bits_sim_cfg.hjson
 @@ -7,7 +7,7 @@
    variant: rng_4bits
- 
+
    // Import the base entropy_src sim_cfg file
 -  import_cfgs: ["{proj_root}/hw/ip/entropy_src/dv/entropy_src_base_sim_cfg.hjson"]
 +  import_cfgs: ["{proj_root}/hw/vendor/lowrisc_ip/ip/entropy_src/dv/entropy_src_base_sim_cfg.hjson"]
- 
+
    build_opts: ["+define+RNG_BUS_WIDTH=4",
                 "+define+RNG_BUS_BIT_SEL_WIDTH=2",

hw/vendor/patches/lowrisc_ip/gpio/0001_fix_paths_and_tool.patch

@@ -19,38 +19,3 @@ index c8a6fdd..8049038 100644
                       "gpio_sec_cm_testplan.hjson"]
    testpoints: [
      {
-diff --git a/dv/gpio_sim_cfg.hjson.tpl b/dv/gpio_sim_cfg.hjson.tpl
-index 9a24e9b..fd51546 100644
---- a/dv/gpio_sim_cfg.hjson.tpl
-+++ b/dv/gpio_sim_cfg.hjson.tpl
-@@ -12,7 +12,7 @@
-   tb: tb
-
-   // Simulator used to sign off this block
--  tool: vcs
-+  tool: xcelium
-
-   // Fusesoc core file used for building the file list.
-   fusesoc_core: ${instance_vlnv(f"lowrisc:dv:{module_instance_name}_sim:0.1")}
-@@ -26,14 +26,14 @@
-
-   // Import additional common sim cfg files.
-   import_cfgs: [// Project wide common sim cfg file
--                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
-                 // Common CIP test lists
--                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
--                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
--                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
--                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
--                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
--                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson"]
-
-   // Add additional tops for simulation.
-   sim_tops: ["${module_instance_name}_bind", "sec_cm_prim_onehot_check_bind"]

hw/vendor/patches/lowrisc_ip/gpio_dv/0001_fix_paths_and_tool.patch

@@ -0,0 +1,35 @@
+diff --git a/gpio_sim_cfg.hjson.tpl b/gpio_sim_cfg.hjson.tpl
+index 9a24e9b..fd51546 100644
+--- a/gpio_sim_cfg.hjson.tpl
++++ b/gpio_sim_cfg.hjson.tpl
+@@ -12,7 +12,7 @@
+   tb: tb
+
+   // Simulator used to sign off this block
+-  tool: vcs
++  tool: xcelium
+
+   // Fusesoc core file used for building the file list.
+   fusesoc_core: ${instance_vlnv(f"lowrisc:dv:{module_instance_name}_sim:0.1")}
+@@ -26,14 +26,14 @@
+
+   // Import additional common sim cfg files.
+   import_cfgs: [// Project wide common sim cfg file
+-                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
+                 // Common CIP test lists
+-                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
+-                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
+-                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
+-                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
+-                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
+-                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
++                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/stress_tests.hjson"]
+
+   // Add additional tops for simulation.
+   sim_tops: ["${module_instance_name}_bind", "sec_cm_prim_onehot_check_bind"]

hw/vendor/patches/lowrisc_ip/i2c/0001-Fix-Paths-and-Tool.patch

@@ -17,59 +17,3 @@ index 1fc121e..a6a2c84 100644
                       "i2c_sec_cm_testplan.hjson"]
    testpoints: [
      //-----------------------------------------------
-diff --git a/dv/i2c_sim_cfg.hjson b/dv/i2c_sim_cfg.hjson
-index 392dba0..db081a6 100644
---- a/dv/i2c_sim_cfg.hjson
-+++ b/dv/i2c_sim_cfg.hjson
-@@ -12,32 +12,32 @@
-   tb: tb
-
-   // Simulator used to sign off this block
--  tool: vcs
-+  tool: xcelium
-
-   // Fusesoc core file used for building the file list.
-   fusesoc_core: lowrisc:dv:i2c_sim:0.1
-
-   // Testplan hjson file.
--  testplan: "{proj_root}/hw/ip/i2c/data/i2c_testplan.hjson"
-+  testplan: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c_testplan.hjson"
-
-   // RAL spec - used to generate the RAL model.
--  ral_spec: "{proj_root}/hw/ip/i2c/data/i2c.hjson"
-+  ral_spec: "{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/data/i2c.hjson"
-
-   // Import additional common sim cfg files.
-   import_cfgs: [// Project wide common sim cfg file
--                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
-                 // Common CIP test lists
--                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
--                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
--                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
--                "{proj_root}/hw/dv/tools/dvsim/tests/sec_cm_tests.hjson",
--                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson"]
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/csr_tests.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/alert_test.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/intr_test.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/sec_cm_tests.hjson",
-+                "{proj_root}/hw/vendor/lowrisc_ip/dv/tools/dvsim/tests/tl_access_tests.hjson"]
-
-   // Add additional tops for simulation.
-   sim_tops: ["i2c_bind", "sec_cm_prim_onehot_check_bind"]
-
-   // Add coverage exclusion file
--  vcs_cov_excl_files: ["{proj_root}/hw/ip/i2c/dv/cov/i2c_cov_excl.el"]
-+  vcs_cov_excl_files: ["{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/i2c_cov_excl.el"]
-
-   // Default iterations for all tests - each test entry can override this.
-   reseed: 50
-@@ -53,7 +53,7 @@
-   overrides: [
-     {
-       name: default_vcs_cov_cfg_file
--      value: "-cm_hier {proj_root}/hw/dv/tools/vcs/cover.cfg+{proj_root}/hw/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/ip/i2c/dv/cov/cov_excl.cfg"
-+      value: "-cm_hier {proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/cover.cfg+{proj_root}/hw/vendor/lowrisc_ip/dv/tools/vcs/common_cov_excl.cfg+{proj_root}/hw/vendor/lowrisc_ip/ip/i2c/dv/cov/cov_excl.cfg"
-     }
-   ]
-