Catch more fetch errors

Author: losfair

src/main/scala/magicore/control/Machine.scala

@@ -159,7 +159,7 @@ object FullMachineException {
 }
 
 object MachineExceptionCode extends SpinalEnum(binarySequential) {
-  val BRANCH_MISS, INSN_CACHE_MISS, DECODE_ERROR, DIVIDE_ERROR, SERIALIZE,
+  val BRANCH_MISS, INSN_CACHE_MISS, INSN_MEMORY_ERROR, DECODE_ERROR, DIVIDE_ERROR, SERIALIZE,
       MEMORY_ERROR, INSN_CACHE_FLUSH, EXCEPTION_RETURN, INSN_ALIGNMENT_ERROR,
       LOAD_ALIGNMENT_ERROR, STORE_ALIGNMENT_ERROR, EXT_INTERRUPT, ENV_CALL, WFI,
       RETRY = newElement()

src/main/scala/magicore/frontend/FetchUnit.scala

@@ -40,6 +40,8 @@ case class FetchPacket(hasInsn: Boolean = true)
   private val fspec = Machine.get[FrontendSpec]
   def parentObjects = Seq()
 
+  val cacheError = Bool()
+
   val cacheMiss = Bool()
   val cacheMissOffset =
     if (fspec.compressed) UInt(log2Up(fspec.addrStep) bits) else null
@@ -231,6 +233,8 @@ case class FetchUnit() extends Area {
 
     private val data = FetchPacket()
 
+    data.cacheError := icache.io.cpu.fetch.error
+
     // `cacheMiss` can be `X` on the first cycle.
     // XXX: Review this.
     data.cacheMiss := icache.io.cpu.fetch.cacheMiss || icache.io.cpu.prefetch.haltIt
@@ -252,6 +256,9 @@ case class FetchUnit() extends Area {
     icache.io.cpu.fetch.isStuck := dataStream.isStall
     icache.io.cpu.fetch.isRemoved := False // ???
     icache.io.cpu.fetch.mmuRsp.physicalAddress := pcFetchStage.pc & fspec.addrMask
+    icache.io.cpu.fetch.mmuRsp.exception := False
+    icache.io.cpu.fetch.mmuRsp.allowExecute := True
+    icache.io.cpu.fetch.mmuRsp.isPaging := False
 
     val decompressor = Machine.tryGet[FetchDecompressor]
     if (decompressor.isDefined) {

src/main/scala/magicore/isa/riscv/RiscvDecoder.scala

@@ -333,12 +333,26 @@ case class RiscvDecoder(
   ).asUInt =/= 0 || inputStream.payload.unsuppressRd)
   outPatched.assignUnassignedByName(out)
 
+  when(out.fetch.cacheError) {
+    outPatched.fuTag := earlyExceptionPort
+    outPatched.earlyExc.code := MachineExceptionCode.INSN_MEMORY_ERROR
+    wantStall := True
+  }
+
   when(out.fetch.cacheMiss) {
     outPatched.fuTag := earlyExceptionPort
     outPatched.earlyExc.code := MachineExceptionCode.INSN_CACHE_MISS
     wantStall := True
   }
 
+  val pcMisaligned =
+    if (compressed) out.fetch.pc(0) else out.fetch.pc(1 downto 0).orR
+  when(pcMisaligned) {
+    outPatched.fuTag := earlyExceptionPort
+    outPatched.earlyExc.code := MachineExceptionCode.INSN_ALIGNMENT_ERROR
+    wantStall := True
+  }
+
   // Suppress interrupts during micro-op sequences.
   when(intrSvc.trigger && !inputStream.payload.microOp) {
     outPatched.fuTag := earlyExceptionPort

src/main/scala/magicore/isa/riscv/RvCsr.scala

@@ -409,6 +409,14 @@ class RvCsr(staticTagData: => Data) extends FunctionUnit {
               // Load access fault
               restartIntoException(5, exc.memoryError_accessAddr.asUInt)
             }
+            is(MachineExceptionCode.INSN_ALIGNMENT_ERROR) {
+              // Instruction address misaligned
+              restartIntoException(0, 0)
+            }
+            is(MachineExceptionCode.INSN_MEMORY_ERROR) {
+              // Instruction access fault
+              restartIntoException(1, 0)
+            }
             is(MachineExceptionCode.LOAD_ALIGNMENT_ERROR) {
               // Load address misaligned
               restartIntoException(4, exc.memoryError_accessAddr.asUInt)