****** START compiling System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this (MethodHash=a7cc3e5d) Generating code for Windows x64 OPTIONS: compCodeOpt = BLENDED_CODE OPTIONS: compDbgCode = false OPTIONS: compDbgInfo = true OPTIONS: compDbgEnC = false OPTIONS: compProcedureSplitting = false OPTIONS: compProcedureSplittingEH = false OPTIONS: No matching PGO data IL to import: IL_0000 02 ldarg.0 IL_0001 7b fb 13 00 04 ldfld 0x40013FB IL_0006 25 dup IL_0007 2d 02 brtrue.s 2 (IL_000b) IL_0009 26 pop IL_000a 2a ret IL_000b 02 ldarg.0 IL_000c 04 ldarg.2 IL_000d 6f ba 24 00 06 callvirt 0x60024BA IL_0012 2a ret lvaSetClass: setting class for V00 to (00007FFB96AE7C40) System.Xml.Schema.XmlSchemaObjectCollection 'this' passed in register rcx Arg #1 passed in register(s) rdx lvaSetClass: setting class for V02 to (00007FFB95A295A8) System.Object Arg #2 passed in register(s) r8 lvaGrabTemp returning 3 (V03 tmp0) (a long lifetime temp) called for OutgoingArgSpace. ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 int ; V02 arg2 ref class-hnd ; V03 OutArgs lclBlk "OutgoingArgSpace" *************** In compInitDebuggingInfo() for System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this getVars() returned cVars = 0, extendOthers = true info.compVarScopesCount = 3 VarNum LVNum Name Beg End 0: 00h 00h V00 this 000h 013h 1: 01h 01h V01 arg1 000h 013h 2: 02h 02h V02 arg2 000h 013h info.compStmtOffsetsCount = 0 info.compStmtOffsetsImplicit = 0005h ( STACK_EMPTY CALL_SITE ) *************** In fgFindBasicBlocks() for System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this Jump targets: IL_000b New Basic Block BB01 [0000] created. BB01 [000..009) New Basic Block BB02 [0001] created. BB02 [009..00B) New Basic Block BB03 [0002] created. BB03 [00B..013) IL Code Size,Instr 19, 10, Basic Block count 3, Local Variable Num,Ref count 4, 3 for method System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this OPTIONS: opts.MinOpts() == false Basic block list for 'System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this' ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) BB02 [0001] 1 1 [009..00B) (return) BB03 [0002] 1 1 [00B..013) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Pre-import *************** Finishing PHASE Pre-import Trees after Pre-import ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) BB02 [0001] 1 1 [009..00B) (return) BB03 [0002] 1 1 [00B..013) (return) ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ------------ BB02 [009..00B) (return), preds={} succs={} ------------ BB03 [00B..013) (return), preds={} succs={} ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Profile incorporation BBOPT set, but no profile data available (hr=80004001) *************** Finishing PHASE Profile incorporation [no changes] *************** Starting PHASE Importation *************** In impImport() for System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this impImportBlockPending for BB01 Importing BB01 (PC=000) of 'System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this' [ 0] 0 (0x000) ldarg.0 [ 1] 1 (0x001) ldfld 040013FB [ 1] 6 (0x006) dup lvaGrabTemp returning 4 (V04 tmp1) called for dup spill. STMT00000 ( 0x000[E-] ... ??? ) [000003] -A-XG------ ▌ ASG ref [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG------ └──▌ FIELD ref _parent [000000] ----------- └──▌ LCL_VAR ref V00 this Marked V04 as a single def local Querying runtime about current class of field System.Xml.Schema.XmlSchemaObjectCollection._parent (declared as System.Xml.Schema.XmlSchemaObject) Field's current class not available lvaSetClass: setting class for V04 to (00007FFB96A9B838) System.Xml.Schema.XmlSchemaObject [ 2] 7 (0x007) brtrue.s STMT00001 ( ??? ... ??? ) [000008] ----------- ▌ JTRUE void [000007] ----------- └──▌ NE int [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 [000006] ----------- └──▌ CNS_INT ref null *************** In impGetSpillTmpBase(BB01) lvaGrabTemps(1) returning 5..5 (long lifetime temps) called for IL Stack Entries *************** In fgComputeCheapPreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) BB02 [0001] 1 1 [009..00B) (return) BB03 [0002] 1 1 [00B..013) (return) ----------------------------------------------------------------------------------------------------------------------------------------- *************** After fgComputeCheapPreds() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd cheap preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) BB02 [0001] 1 BB01 1 [009..00B) (return) BB03 [0002] 1 BB01 1 [00B..013) (return) ----------------------------------------------------------------------------------------------------------------------------------------- Spilling stack entries into temps STMT00002 ( ??? ... ??? ) [000010] -A--------- ▌ ASG ref [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 STMT00001 ( ??? ... ??? ) [000008] ----------- ▌ JTRUE void [000007] ----------- └──▌ NE int [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 [000006] ----------- └──▌ CNS_INT ref null impImportBlockPending for BB02 impImportBlockPending for BB03 Importing BB03 (PC=011) of 'System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this' [ 1] 11 (0x00b) ldarg.0 [ 2] 12 (0x00c) ldarg.2 [ 3] 13 (0x00d) callvirt 060024BA (Implicit Tail call: prefixFlags |= PREFIX_TAILCALL_IMPLICIT) In Compiler::impImportCall: opcode is callvirt, kind=4, callRetType is void, structSize is 0 impDevirtualizeCall: no type available (op=LCL_VAR) Considering guarded devirtualization at IL offset 13 (0xd) Not guessing for class or method: no GDV profile pgo data, or pgo disabled GTF_CALL_M_IMPLICIT_TAILCALL set for call [000016] INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' for 'System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this' calling 'System.Xml.Schema.XmlSchemaObject:hackishMethodName' INLINER: during 'impMarkInlineCandidate' result 'failed this call site' reason 'target not direct' STMT00003 ( ??? ... ??? ) [000016] --C-G------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000013] ----------- this ├──▌ LCL_VAR ref V05 tmp2 [000014] ----------- arg1 ├──▌ LCL_VAR ref V00 this [000015] ----------- arg2 └──▌ LCL_VAR ref V02 arg2 [ 0] 18 (0x012) ret STMT00004 ( 0x012[E-] ... ??? ) [000017] ----------- ▌ RETURN void Importing BB02 (PC=009) of 'System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this' [ 1] 9 (0x009) pop [ 0] 10 (0x00a) ret STMT00005 ( 0x00A[E-] ... ??? ) [000018] ----------- ▌ RETURN void *************** Finishing PHASE Importation Trees after Importation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 1 [009..00B) (return) i BB03 [0002] 1 1 [00B..013) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000003] -A-XG------ ▌ ASG ref [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG------ └──▌ FIELD ref _parent [000000] ----------- └──▌ LCL_VAR ref V00 this ***** BB01 STMT00002 ( ??? ... 0x007 ) [000010] -A--------- ▌ ASG ref [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 ***** BB01 STMT00001 ( ??? ... ??? ) [000008] ----------- ▌ JTRUE void [000007] ----------- └──▌ NE int [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 [000006] ----------- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) [000018] ----------- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) [000016] --C-G------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000013] ----------- this ├──▌ LCL_VAR ref V05 tmp2 [000014] ----------- arg1 ├──▌ LCL_VAR ref V00 this [000015] ----------- arg2 └──▌ LCL_VAR ref V02 arg2 ***** BB03 STMT00004 ( 0x012[E-] ... ??? ) [000017] ----------- ▌ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Expand patchpoints -- no patchpoints to transform *************** Finishing PHASE Expand patchpoints [no changes] *************** Starting PHASE Indirect call transform -- no candidates to transform *************** Finishing PHASE Indirect call transform [no changes] *************** Starting PHASE Post-import *************** Finishing PHASE Post-import [no changes] *************** Starting PHASE Morph - Init New BlockSet epoch 1, # of blocks (including unused BB00): 4, bitset array size: 1 (short) *************** Finishing PHASE Morph - Init [no changes] *************** Starting PHASE Morph - Inlining *************** In fgDebugCheckBBlist Querying runtime about current class of field System.Xml.Schema.XmlSchemaObjectCollection._parent (declared as System.Xml.Schema.XmlSchemaObject) Field's current class not available INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target not direct' for 'System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this' calling 'System.Xml.Schema.XmlSchemaObject:hackishMethodName' INLINER: during 'fgNoteNonInlineCandidate' result 'failed this call site' reason 'target not direct' **** Late devirt opportunity [000016] --C-G------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000013] ----------- this ├──▌ LCL_VAR ref V05 tmp2 [000014] ----------- arg1 ├──▌ LCL_VAR ref V00 this [000015] ----------- arg2 └──▌ LCL_VAR ref V02 arg2 impDevirtualizeCall: no type available (op=LCL_VAR) No guarded devirt during late devirtualization **************** Inline Tree Inlines into 06000000 [via ExtendedDefaultPolicy] System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this: [INL00 IL=0013 TR=000016 06000000] [FAILED: call site: target not direct] System.Xml.Schema.XmlSchemaObject:hackishMethodName Budget: initialTime=117, finalTime=117, initialBudget=1170, currentBudget=1170 Budget: initialSize=564, finalSize=564 *************** Finishing PHASE Morph - Inlining Trees after Morph - Inlining ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 1 [009..00B) (return) i BB03 [0002] 1 1 [00B..013) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000003] -A-XG------ ▌ ASG ref [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG------ └──▌ FIELD ref _parent [000000] ----------- └──▌ LCL_VAR ref V00 this ***** BB01 STMT00002 ( ??? ... 0x007 ) [000010] -A--------- ▌ ASG ref [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 ***** BB01 STMT00001 ( ??? ... ??? ) [000008] ----------- ▌ JTRUE void [000007] ----------- └──▌ NE int [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 [000006] ----------- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) [000018] ----------- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) [000016] --C-G------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000013] ----------- this ├──▌ LCL_VAR ref V05 tmp2 [000014] ----------- arg1 ├──▌ LCL_VAR ref V00 this [000015] ----------- arg2 └──▌ LCL_VAR ref V02 arg2 ***** BB03 STMT00004 ( 0x012[E-] ... ??? ) [000017] ----------- ▌ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Allocate Objects no newobjs in this method; punting *************** Finishing PHASE Allocate Objects [no changes] *************** Starting PHASE Morph - Add internal blocks *************** After fgAddInternal() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 1 [009..00B) (return) i BB03 [0002] 1 1 [00B..013) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** Finishing PHASE Morph - Add internal blocks [no changes] *************** Starting PHASE Remove empty try *************** In fgRemoveEmptyTry() No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty try [no changes] *************** Starting PHASE Remove empty finally No EH in this method, nothing to remove. *************** Finishing PHASE Remove empty finally [no changes] *************** Starting PHASE Merge callfinally chains No EH in this method, nothing to merge. *************** Finishing PHASE Merge callfinally chains [no changes] *************** Starting PHASE Clone finally No EH in this method, no cloning. *************** Finishing PHASE Clone finally [no changes] *************** Starting PHASE Compute preds Renumbering the basic blocks for fgComputePred *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 1 [009..00B) (return) i BB03 [0002] 1 1 [00B..013) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! Setting edge weights for BB01 -> BB03 to [0 .. 3.402823e+38] Setting edge weights for BB01 -> BB02 to [0 .. 3.402823e+38] *************** Finishing PHASE Compute preds Trees after Compute preds ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [009..00B) (return) i BB03 [0002] 1 BB01 1 [00B..013) (return) i ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000003] -A-XG------ ▌ ASG ref [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG------ └──▌ FIELD ref _parent [000000] ----------- └──▌ LCL_VAR ref V00 this ***** BB01 STMT00002 ( ??? ... 0x007 ) [000010] -A--------- ▌ ASG ref [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 ***** BB01 STMT00001 ( ??? ... ??? ) [000008] ----------- ▌ JTRUE void [000007] ----------- └──▌ NE int [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 [000006] ----------- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) [000018] ----------- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) [000016] --C-G------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000013] ----------- this ├──▌ LCL_VAR ref V05 tmp2 [000014] ----------- arg1 ├──▌ LCL_VAR ref V00 this [000015] ----------- arg2 └──▌ LCL_VAR ref V02 arg2 ***** BB03 STMT00004 ( 0x012[E-] ... ??? ) [000017] ----------- ▌ RETURN void ------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Merge throw blocks *************** In fgTailMergeThrows Method does not have multiple noreturn calls. *************** Finishing PHASE Merge throw blocks [no changes] *************** Starting PHASE Update flow graph early pass *************** Finishing PHASE Update flow graph early pass [no changes] *************** Starting PHASE Morph - Promote Structs lvaTable before fgPromoteStructs ; Initial local variable assignments ; ; V00 this ref this class-hnd ; V01 arg1 int ; V02 arg2 ref class-hnd ; V03 OutArgs lclBlk "OutgoingArgSpace" ; V04 tmp1 ref class-hnd "dup spill" ; V05 tmp2 ref *************** Finishing PHASE Morph - Promote Structs [no changes] *************** Starting PHASE Morph - Structs/AddrExp LocalAddressVisitor visiting statement: STMT00000 ( 0x000[E-] ... 0x007 ) [000003] -A-XG------ ▌ ASG ref [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG------ └──▌ FIELD ref _parent [000000] ----------- └──▌ LCL_VAR ref V00 this LocalAddressVisitor visiting statement: STMT00002 ( ??? ... 0x007 ) [000010] -A--------- ▌ ASG ref [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 LocalAddressVisitor visiting statement: STMT00001 ( ??? ... ??? ) [000008] ----------- ▌ JTRUE void [000007] ----------- └──▌ NE int [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 [000006] ----------- └──▌ CNS_INT ref null LocalAddressVisitor visiting statement: STMT00005 ( 0x00A[E-] ... 0x00A ) [000018] ----------- ▌ RETURN void LocalAddressVisitor visiting statement: STMT00003 ( ??? ... 0x012 ) [000016] --C-G------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000013] ----------- this ├──▌ LCL_VAR ref V05 tmp2 [000014] ----------- arg1 ├──▌ LCL_VAR ref V00 this [000015] ----------- arg2 └──▌ LCL_VAR ref V02 arg2 LocalAddressVisitor visiting statement: STMT00004 ( 0x012[E-] ... ??? ) [000017] ----------- ▌ RETURN void *************** Finishing PHASE Morph - Structs/AddrExp [no changes] *************** Starting PHASE Forward Substitution ===> BB01 [000003]: not asg (single-use lcl) [000010]: no next stmt use ===> BB02 ===> BB03 *************** Finishing PHASE Forward Substitution [no changes] *************** Starting PHASE Morph - ByRefs *************** Finishing PHASE Morph - ByRefs [no changes] *************** Starting PHASE Morph - Global *************** In fgMorphBlocks() Morphing BB01 of 'System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this' fgMorphTree BB01, STMT00000 (before) [000003] -A-XG------ ▌ ASG ref [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG------ └──▌ FIELD ref _parent [000000] ----------- └──▌ LCL_VAR ref V00 this Notify VM instruction set (SSE2) must be supported. Final value of Compiler::fgMorphField after calling fgMorphSmpOp: [000001] ---XG------ ▌ IND ref [000020] -----+----- └──▌ ADD byref [000000] -----+----- ├──▌ LCL_VAR ref V00 this [000019] -----+----- └──▌ CNS_INT long 16 Fseq[_parent] GenTreeNode creates assertion: [000001] ---XG+----- ▌ IND ref In BB01 New Local Constant Assertion: V00 != null, index = #01 fgMorphTree BB01, STMT00000 (after) [000003] -A-XG+----- ▌ ASG ref [000002] D----+-N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG+----- └──▌ IND ref [000020] -----+----- └──▌ ADD byref [000000] -----+----- ├──▌ LCL_VAR ref V00 this [000019] -----+----- └──▌ CNS_INT long 16 Fseq[_parent] fgMorphTree BB01, STMT00002 (before) [000010] -A--------- ▌ ASG ref [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 GenTreeNode creates assertion: [000010] -A---+----- ▌ ASG ref In BB01 New Local Copy Assertion: V05 == V04, index = #02 fgMorphTree BB01, STMT00001 (before) [000008] ----------- ▌ JTRUE void [000007] ----------- └──▌ NE int [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 [000006] ----------- └──▌ CNS_INT ref null Morphing BB02 of 'System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this' fgMorphTree BB02, STMT00005 (before) [000018] ----------- ▌ RETURN void Morphing BB03 of 'System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this' fgMorphTree BB03, STMT00003 (before) [000016] --C-G------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000013] ----------- this ├──▌ LCL_VAR ref V05 tmp2 [000014] ----------- arg1 ├──▌ LCL_VAR ref V00 this [000015] ----------- arg2 └──▌ LCL_VAR ref V02 arg2 Initializing arg info for 16.CALL: Args for call [000016] CALL after AddFinalArgsAndDetermineABIInfo: CallArg[[000013].LCL_VAR ref (By value), 1 reg: rcx, byteAlignment=8, wellKnown[ThisPointer]] CallArg[[000014].LCL_VAR ref (By value), 1 reg: rdx, byteAlignment=8] CallArg[[000015].LCL_VAR ref (By value), 1 reg: r8, byteAlignment=8] [Fast tailcall decision]: Will fast tailcall GTF_CALL_M_TAILCALL bit set for call [000016] Remove all stmts after the call. removing useless STMT00004 ( 0x012[E-] ... ??? ) [000017] ----------- ▌ RETURN void from BB03 Morphing args for 16.CALL: Sorting the arguments: Arguments have register interference. Argument order and SCCs: [ [000014] ] [ [000013] ] [ [000015] ] Deferred argument ('rdx'): [000014] -----+----- ▌ LCL_VAR ref V00 this Moved to late list Deferred argument ('rcx'): [000013] -----+----- ▌ LCL_VAR ref V05 tmp2 Moved to late list Deferred argument ('r8'): [000015] -----+----- ▌ LCL_VAR ref V02 arg2 Moved to late list Register placement order: rdx rcx r8 Args for [000016].CALL after fgMorphArgs: CallArg[[000013].LCL_VAR ref (By value), 1 reg: rcx, byteAlignment=8, isLate, wellKnown[ThisPointer]] CallArg[[000014].LCL_VAR ref (By value), 1 reg: rdx, byteAlignment=8, isLate] CallArg[[000015].LCL_VAR ref (By value), 1 reg: r8, byteAlignment=8, isLate] OutgoingArgsStackSize is 32 Expanding virtual call target for 16.CALL: GenTreeNode creates assertion: [000022] #--X-+----- ▌ IND long In BB03 New Local Constant Assertion: V05 != null, index = #01 *************** In fgMarkDemotedImplicitByRefArgs() *************** Finishing PHASE Morph - Global Trees after Morph - Global ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [009..00B) (return) i BB03 [0002] 1 BB01 1 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000003] -A-XG+----- ▌ ASG ref [000002] D----+-N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG+----- └──▌ IND ref [000020] -----+----- └──▌ ADD byref [000000] -----+----- ├──▌ LCL_VAR ref V00 this [000019] -----+----- └──▌ CNS_INT long 16 Fseq[_parent] ***** BB01 STMT00002 ( ??? ... 0x007 ) [000010] -A---+----- ▌ ASG ref [000009] D----+-N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] -----+----- └──▌ LCL_VAR ref V04 tmp1 ***** BB01 STMT00001 ( ??? ... ??? ) [000008] -----+----- ▌ JTRUE void [000007] J----+-N--- └──▌ NE int [000005] -----+----- ├──▌ LCL_VAR ref V04 tmp1 [000006] -----+----- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) [000018] -----+----- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) [000016] --CXG+----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000028] n--X-+----- control expr └──▌ IND long [000027] ---X-+----- └──▌ ADD long [000025] #--X-+----- ├──▌ IND long [000024] ---X-+----- │ └──▌ ADD long [000022] #--X-+----- │ ├──▌ IND long [000021] -----+----- │ │ └──▌ LCL_VAR ref V05 tmp2 [000023] -----+----- │ └──▌ CNS_INT long 72 [000026] -----+----- └──▌ CNS_INT long 32 [000014] -----+----- arg1 in rdx ├──▌ LCL_VAR ref V00 this [000013] -----+----- this in rcx ├──▌ LCL_VAR ref V05 tmp2 [000015] -----+----- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE GS Cookie No GS security needed *************** Finishing PHASE GS Cookie [no changes] *************** Starting PHASE Compute edge weights (1, false) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [009..00B) (return) i BB03 [0002] 1 BB01 1 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- -- no profile data, so using default called count -- not optimizing or no profile data, so not computing edge weights *************** Finishing PHASE Compute edge weights (1, false) [no changes] *************** Starting PHASE Create EH funclets *************** Finishing PHASE Create EH funclets [no changes] *************** Starting PHASE Invert loops *************** Finishing PHASE Invert loops [no changes] *************** Starting PHASE Optimize control flow *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [009..00B) (return) i BB03 [0002] 1 BB01 1 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [009..00B) (return) i BB03 [0002] 1 BB01 1 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [009..00B) (return) i BB03 [0002] 1 BB01 1 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize control flow Trees after Optimize control flow ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [009..00B) (return) i BB03 [0002] 1 BB01 1 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000003] -A-XG+----- ▌ ASG ref [000002] D----+-N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG+----- └──▌ IND ref [000020] -----+----- └──▌ ADD byref [000000] -----+----- ├──▌ LCL_VAR ref V00 this [000019] -----+----- └──▌ CNS_INT long 16 Fseq[_parent] ***** BB01 STMT00002 ( ??? ... 0x007 ) [000010] -A---+----- ▌ ASG ref [000009] D----+-N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] -----+----- └──▌ LCL_VAR ref V04 tmp1 ***** BB01 STMT00001 ( ??? ... ??? ) [000008] -----+----- ▌ JTRUE void [000007] J----+-N--- └──▌ NE int [000005] -----+----- ├──▌ LCL_VAR ref V04 tmp1 [000006] -----+----- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) [000018] -----+----- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) [000016] --CXG+----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000028] n--X-+----- control expr └──▌ IND long [000027] ---X-+----- └──▌ ADD long [000025] #--X-+----- ├──▌ IND long [000024] ---X-+----- │ └──▌ ADD long [000022] #--X-+----- │ ├──▌ IND long [000021] -----+----- │ │ └──▌ LCL_VAR ref V05 tmp2 [000023] -----+----- │ └──▌ CNS_INT long 72 [000026] -----+----- └──▌ CNS_INT long 32 [000014] -----+----- arg1 in rdx ├──▌ LCL_VAR ref V00 this [000013] -----+----- this in rcx ├──▌ LCL_VAR ref V05 tmp2 [000015] -----+----- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Compute blocks reachability Return blocks: BB03 BB02 Renumbering the basic blocks for fgComputeReachability pass #1 *************** Before renumbering the basic blocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 1 [009..00B) (return) i BB03 [0002] 1 BB01 1 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty *************** After renumbering the basic blocks =============== No blocks renumbered! Enter blocks: BB01 After computing reachability sets: ------------------------------------------------ BBnum Reachable by ------------------------------------------------ BB01 : BB01 BB02 : BB01 BB02 BB03 : BB01 BB03 *************** In fgComputeDoms *************** In fgDebugCheckBBlist Dominator computation start blocks (those blocks with no incoming edges): BB01 ------------------------------------------------ BBnum Dominated by ------------------------------------------------ BB01: BB01 BB02: BB02 BB01 BB03: BB03 BB01 Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB03 BB02 After numbering the dominator tree: BB01: pre=01, post=03 BB02: pre=03, post=02 BB03: pre=02, post=01 *************** Finishing PHASE Compute blocks reachability [no changes] *************** Starting PHASE Set block weights *************** Finishing PHASE Set block weights Trees after Set block weights ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000003] -A-XG+----- ▌ ASG ref [000002] D----+-N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG+----- └──▌ IND ref [000020] -----+----- └──▌ ADD byref [000000] -----+----- ├──▌ LCL_VAR ref V00 this [000019] -----+----- └──▌ CNS_INT long 16 Fseq[_parent] ***** BB01 STMT00002 ( ??? ... 0x007 ) [000010] -A---+----- ▌ ASG ref [000009] D----+-N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] -----+----- └──▌ LCL_VAR ref V04 tmp1 ***** BB01 STMT00001 ( ??? ... ??? ) [000008] -----+----- ▌ JTRUE void [000007] J----+-N--- └──▌ NE int [000005] -----+----- ├──▌ LCL_VAR ref V04 tmp1 [000006] -----+----- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) [000018] -----+----- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) [000016] --CXG+----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000028] n--X-+----- control expr └──▌ IND long [000027] ---X-+----- └──▌ ADD long [000025] #--X-+----- ├──▌ IND long [000024] ---X-+----- │ └──▌ ADD long [000022] #--X-+----- │ ├──▌ IND long [000021] -----+----- │ │ └──▌ LCL_VAR ref V05 tmp2 [000023] -----+----- │ └──▌ CNS_INT long 72 [000026] -----+----- └──▌ CNS_INT long 32 [000014] -----+----- arg1 in rdx ├──▌ LCL_VAR ref V00 this [000013] -----+----- this in rcx ├──▌ LCL_VAR ref V05 tmp2 [000015] -----+----- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Find loops *************** In optFindLoops() *************** In optMarkLoopHeads() 0 loop heads marked *************** Finishing PHASE Find loops Trees after Find loops ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) [000003] -A-XG+----- ▌ ASG ref [000002] D----+-N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG+----- └──▌ IND ref [000020] -----+----- └──▌ ADD byref [000000] -----+----- ├──▌ LCL_VAR ref V00 this [000019] -----+----- └──▌ CNS_INT long 16 Fseq[_parent] ***** BB01 STMT00002 ( ??? ... 0x007 ) [000010] -A---+----- ▌ ASG ref [000009] D----+-N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] -----+----- └──▌ LCL_VAR ref V04 tmp1 ***** BB01 STMT00001 ( ??? ... ??? ) [000008] -----+----- ▌ JTRUE void [000007] J----+-N--- └──▌ NE int [000005] -----+----- ├──▌ LCL_VAR ref V04 tmp1 [000006] -----+----- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) [000018] -----+----- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) [000016] --CXG+----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000028] n--X-+----- control expr └──▌ IND long [000027] ---X-+----- └──▌ ADD long [000025] #--X-+----- ├──▌ IND long [000024] ---X-+----- │ └──▌ ADD long [000022] #--X-+----- │ ├──▌ IND long [000021] -----+----- │ │ └──▌ LCL_VAR ref V05 tmp2 [000023] -----+----- │ └──▌ CNS_INT long 72 [000026] -----+----- └──▌ CNS_INT long 32 [000014] -----+----- arg1 in rdx ├──▌ LCL_VAR ref V00 this [000013] -----+----- this in rcx ├──▌ LCL_VAR ref V05 tmp2 [000015] -----+----- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Clone loops *************** In optCloneLoops() No loops to clone *************** Finishing PHASE Clone loops [no changes] *************** Starting PHASE Unroll loops *************** Finishing PHASE Unroll loops [no changes] *************** Starting PHASE Clear loop info *************** Finishing PHASE Clear loop info [no changes] *************** Starting PHASE Morph array ops No multi-dimensional array references in the function *************** Finishing PHASE Morph array ops [no changes] *************** Starting PHASE Mark local vars *************** In lvaMarkLocalVars() *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** *** marking local variables in block BB01 (weight=1 ) STMT00000 ( 0x000[E-] ... 0x007 ) [000003] -A-XG+----- ▌ ASG ref [000002] D----+-N--- ├──▌ LCL_VAR ref V04 tmp1 [000001] ---XG+----- └──▌ IND ref [000020] -----+----- └──▌ ADD byref [000000] -----+----- ├──▌ LCL_VAR ref V00 this [000019] -----+----- └──▌ CNS_INT long 16 Fseq[_parent] New refCnts for V04: refCnt = 1, refCntWtd = 2 Marking EH Var V04 as a register candidate. New refCnts for V00: refCnt = 1, refCntWtd = 1 STMT00002 ( ??? ... 0x007 ) [000010] -A---+----- ▌ ASG ref [000009] D----+-N--- ├──▌ LCL_VAR ref V05 tmp2 [000004] -----+----- └──▌ LCL_VAR ref V04 tmp1 New refCnts for V05: refCnt = 1, refCntWtd = 1 Marking EH Var V05 as a register candidate. New refCnts for V04: refCnt = 2, refCntWtd = 4 STMT00001 ( ??? ... ??? ) [000008] -----+----- ▌ JTRUE void [000007] J----+-N--- └──▌ NE int [000005] -----+----- ├──▌ LCL_VAR ref V04 tmp1 [000006] -----+----- └──▌ CNS_INT ref null New refCnts for V04: refCnt = 3, refCntWtd = 6 *** marking local variables in block BB02 (weight=0.50) STMT00005 ( 0x00A[E-] ... 0x00A ) [000018] -----+----- ▌ RETURN void *** marking local variables in block BB03 (weight=0.50) STMT00003 ( ??? ... 0x012 ) [000016] --CXG+----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName [000028] n--X-+----- control expr └──▌ IND long [000027] ---X-+----- └──▌ ADD long [000025] #--X-+----- ├──▌ IND long [000024] ---X-+----- │ └──▌ ADD long [000022] #--X-+----- │ ├──▌ IND long [000021] -----+----- │ │ └──▌ LCL_VAR ref V05 tmp2 [000023] -----+----- │ └──▌ CNS_INT long 72 [000026] -----+----- └──▌ CNS_INT long 32 [000014] -----+----- arg1 in rdx ├──▌ LCL_VAR ref V00 this [000013] -----+----- this in rcx ├──▌ LCL_VAR ref V05 tmp2 [000015] -----+----- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 New refCnts for V00: refCnt = 2, refCntWtd = 1.50 New refCnts for V05: refCnt = 2, refCntWtd = 1.50 New refCnts for V02: refCnt = 1, refCntWtd = 0.50 New refCnts for V05: refCnt = 3, refCntWtd = 2 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 2.50 New refCnts for V00: refCnt = 4, refCntWtd = 3.50 New refCnts for V02: refCnt = 2, refCntWtd = 1.50 New refCnts for V02: refCnt = 3, refCntWtd = 2.50 *************** Finishing PHASE Mark local vars [no changes] *************** Starting PHASE Opt add copies *************** In optAddCopies() *************** Finishing PHASE Opt add copies [no changes] *************** Starting PHASE Find oper order *************** In fgFindOperOrder() *************** Finishing PHASE Find oper order Trees after Find oper order ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 ( 4, 4) [000001] ---XG------ └──▌ IND ref ( 2, 2) [000020] -------N--- └──▌ ADD byref ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] ***** BB01 STMT00002 ( ??? ... 0x007 ) ( 5, 4) [000010] -A------R-- ▌ ASG ref ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 ***** BB01 STMT00001 ( ??? ... ??? ) ( 5, 5) [000008] ----------- ▌ JTRUE void ( 3, 3) [000007] J------N--- └──▌ NE int ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) ( 0, 0) [000018] ----------- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) ( 39, 25) [000016] --CXG------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName ( 12, 10) [000028] n--X------- control expr └──▌ IND long ( 10, 8) [000027] ---X---N--- └──▌ ADD long ( 9, 7) [000025] #--X------- ├──▌ IND long ( 7, 5) [000024] ---X---N--- │ └──▌ ADD long ( 6, 4) [000022] #--X------- │ ├──▌ IND long ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Set block order *************** In fgSetBlockOrder() The biggest BB has 12 tree nodes *************** Finishing PHASE Set block order Trees after Set block order ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] ***** BB01 STMT00002 ( ??? ... 0x007 ) N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 ***** BB01 STMT00001 ( ??? ... ??? ) N004 ( 5, 5) [000008] ----------- ▌ JTRUE void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) N001 ( 0, 0) [000018] ----------- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) N012 ( 39, 25) [000016] --CXG------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName N011 ( 12, 10) [000028] n--X------- control expr └──▌ IND long N010 ( 10, 8) [000027] ---X---N--- └──▌ ADD long N008 ( 9, 7) [000025] #--X------- ├──▌ IND long N007 ( 7, 5) [000024] ---X---N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #--X------- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Build SSA representation *************** In SsaBuilder::Build() [SsaBuilder] Max block count is 4. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- *************** Exception Handling table is empty [SsaBuilder] Topologically sorted the graph. [SsaBuilder::ComputeImmediateDom] Inside fgBuildDomTree After computing the Dominance Tree: BB01 : BB03 BB02 *************** In fgLocalVarLiveness() In fgLocalVarLivenessInit Tracked variable (4 out of 6) table: V04 tmp1 [ ref]: refCnt = 3, refCntWtd = 6 V00 this [ ref]: refCnt = 4, refCntWtd = 3.50 V02 arg2 [ ref]: refCnt = 3, refCntWtd = 2.50 V05 tmp2 [ ref]: refCnt = 3, refCntWtd = 2 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={ V00 } + ByrefExposed + GcHeap DEF(2)={V04 V05} BB02 USE(0)={} DEF(0)={} BB03 USE(3)={V00 V02 V05} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V00 V02 } + ByrefExposed + GcHeap OUT(3)={V00 V02 V05} + ByrefExposed + GcHeap BB02 IN (0)={} OUT(0)={} BB03 IN (3)={V00 V02 V05} + ByrefExposed + GcHeap OUT(0)={ } *************** In optRemoveRedundantZeroInits() *************** In SsaBuilder::InsertPhiFunctions() Inserting phi functions: *************** In SsaBuilder::RenameVariables() *************** Finishing PHASE Build SSA representation Trees after Build SSA representation ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 d:1 N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] ***** BB01 STMT00002 ( ??? ... 0x007 ) N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 d:1 N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 u:1 ***** BB01 STMT00001 ( ??? ... ??? ) N004 ( 5, 5) [000008] ----------- ▌ JTRUE void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 u:1 (last use) N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) N001 ( 0, 0) [000018] ----------- ▌ RETURN void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) N012 ( 39, 25) [000016] --CXG------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName N011 ( 12, 10) [000028] n--X------- control expr └──▌ IND long N010 ( 10, 8) [000027] ---X---N--- └──▌ ADD long N008 ( 9, 7) [000025] #--X------- ├──▌ IND long N007 ( 7, 5) [000024] ---X---N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #--X------- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Early Value Propagation no arrays or null checks in the method *************** Finishing PHASE Early Value Propagation [no changes] *************** Starting PHASE Do value numbering *************** In fgValueNumber() Memory Initial Value in BB01 is: $c0 The SSA definition for ByrefExposed (#1) at start of BB01 is $c0 {InitVal($42)} The SSA definition for GcHeap (#1) at start of BB01 is $c0 {InitVal($42)} ***** BB01, STMT00000(before) N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 d:1 N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this u:1 N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] N001 [000000] LCL_VAR V00 this u:1 => $80 {InitVal($40)} N002 [000019] CNS_INT 16 Fseq[_parent] => $100 {LngCns: 16} N003 [000020] ADD => $140 {ADD($80, $100)} VNForHandle(_parent) is $180, fieldType is ref, size = 8 VNForMapSelect($c0, $180):mem returns $1c0 {$c0[$180]} VNForMapSelect($1c0, $80):ref returns $200 {$1c0[$80]} N004 [000001] IND => N005 [000002] LCL_VAR V04 tmp1 d:1 => $VN.Void Tree [000003] assigned VN to local var V04/1: N006 [000003] ASG => $204 {norm=$VN.Void, exc=$201 {NullPtrExc($80)}} ***** BB01, STMT00000(after) N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref $204 N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 d:1 $VN.Void N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref $140 N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this u:1 $80 N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] $100 --------- ***** BB01, STMT00002(before) N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 d:1 N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 u:1 N001 [000004] LCL_VAR V04 tmp1 u:1 => N002 [000009] LCL_VAR V05 tmp2 d:1 => $VN.Void Tree [000010] assigned VN to local var V05/1: N003 [000010] ASG => $VN.Void ***** BB01, STMT00002(after) N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref $VN.Void N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 d:1 $VN.Void N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 u:1 --------- ***** BB01, STMT00001(before) N004 ( 5, 5) [000008] ----------- ▌ JTRUE void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 u:1 (last use) N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null N001 [000005] LCL_VAR V04 tmp1 u:1 (last use) => N002 [000006] CNS_INT null => $VN.Null N003 [000007] NE => N004 [000008] JTRUE => $VN.Void ***** BB01, STMT00001(after) N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 u:1 (last use) N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null $VN.Null finish(BB01). Succ(BB02). Not yet completed. All preds complete, adding to allDone. Succ(BB03). Not yet completed. All preds complete, adding to allDone. The SSA definition for ByrefExposed (#1) at start of BB03 is $c0 {InitVal($42)} The SSA definition for GcHeap (#1) at start of BB03 is $c0 {InitVal($42)} ***** BB03, STMT00003(before) N012 ( 39, 25) [000016] --CXG------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName N011 ( 12, 10) [000028] n--X------- control expr └──▌ IND long N010 ( 10, 8) [000027] ---X---N--- └──▌ ADD long N008 ( 9, 7) [000025] #--X------- ├──▌ IND long N007 ( 7, 5) [000024] ---X---N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #--X------- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) N001 [000014] LCL_VAR V00 this u:1 (last use) => $80 {InitVal($40)} N002 [000013] LCL_VAR V05 tmp2 u:1 => N003 [000015] LCL_VAR V02 arg2 u:1 (last use) => $81 {InitVal($41)} N004 [000021] LCL_VAR V05 tmp2 u:1 (last use) => N005 [000022] IND => N006 [000023] CNS_INT 72 => $101 {LngCns: 72} N007 [000024] ADD => N008 [000025] IND => N009 [000026] CNS_INT 32 => $103 {LngCns: 32} N010 [000027] ADD => N011 [000028] IND => fgCurMemoryVN[GcHeap] assigned for CALL at [000016] to VN: $c1. N012 [000016] CALLV vt-ind => $VN.Void ***** BB03, STMT00003(after) N012 ( 39, 25) [000016] --CXG------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void N011 ( 12, 10) [000028] n--X------- control expr └──▌ IND long N010 ( 10, 8) [000027] ---X---N--- └──▌ ADD long N008 ( 9, 7) [000025] #--X------- ├──▌ IND long N007 ( 7, 5) [000024] ---X---N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #--X------- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 $101 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 $103 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) $81 finish(BB03). The SSA definition for ByrefExposed (#1) at start of BB02 is $c0 {InitVal($42)} The SSA definition for GcHeap (#1) at start of BB02 is $c0 {InitVal($42)} ***** BB02, STMT00005(before) N001 ( 0, 0) [000018] ----------- ▌ RETURN void N001 [000018] RETURN => $VN.Void ***** BB02, STMT00005(after) N001 ( 0, 0) [000018] ----------- ▌ RETURN void $VN.Void finish(BB02). *************** Finishing PHASE Do value numbering Trees after Do value numbering ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref $204 N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 d:1 $VN.Void N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref $140 N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this u:1 $80 N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] $100 ***** BB01 STMT00002 ( ??? ... 0x007 ) N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref $VN.Void N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 d:1 $VN.Void N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 u:1 ***** BB01 STMT00001 ( ??? ... ??? ) N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V04 tmp1 u:1 (last use) N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null $VN.Null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) N001 ( 0, 0) [000018] ----------- ▌ RETURN void $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) N012 ( 39, 25) [000016] --CXG------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void N011 ( 12, 10) [000028] n--X------- control expr └──▌ IND long N010 ( 10, 8) [000027] ---X---N--- └──▌ ADD long N008 ( 9, 7) [000025] #--X------- ├──▌ IND long N007 ( 7, 5) [000024] ---X---N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #--X------- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 $101 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 $103 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) $81 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Hoist loop code No loops; no hoisting *************** Finishing PHASE Hoist loop code [no changes] *************** Starting PHASE VN based copy prop Copy Assertion for BB01 curSsaName stack: { } Live vars: {V00 V02} => {V00 V02 V04} Live vars: {V00 V02 V04} => {V00 V02 V04 V05} Live vars: {V00 V02 V04 V05} => {V00 V02 V05} VN based copy assertion for [000005] V04 $82 by [000009] V05 $82. N001 ( 1, 1) [000005] ----------- ▌ LCL_VAR ref V04 tmp1 u:1 (last use) copy propagated to: N001 ( 1, 1) [000005] ----------- ▌ LCL_VAR ref V05 tmp2 u:1 (last use) Copy Assertion for BB03 curSsaName stack: { 0-[000000]:V00 4-[000002]:V04 5-[000009]:V05 } Live vars: {V00 V02 V05} => {V02 V05} Live vars: {V02 V05} => {V05} Live vars: {V05} => {} Copy Assertion for BB02 curSsaName stack: { 0-[000000]:V00 2-[000015]:V02 4-[000002]:V04 5-[000009]:V05 } *************** Finishing PHASE VN based copy prop Trees after VN based copy prop ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref $204 N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 d:1 $VN.Void N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref $140 N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this u:1 $80 N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] $100 ***** BB01 STMT00002 ( ??? ... 0x007 ) N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref $VN.Void N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 d:1 $VN.Void N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 u:1 ***** BB01 STMT00001 ( ??? ... ??? ) N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null $VN.Null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) N001 ( 0, 0) [000018] ----------- ▌ RETURN void $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) N012 ( 39, 25) [000016] --CXG------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void N011 ( 12, 10) [000028] n--X------- control expr └──▌ IND long N010 ( 10, 8) [000027] ---X---N--- └──▌ ADD long N008 ( 9, 7) [000025] #--X------- ├──▌ IND long N007 ( 7, 5) [000024] ---X---N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #--X------- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 $101 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 $103 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) $81 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Redundant branch opts ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- optRedundantRelop in BB01; jump tree is N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null $VN.Null ... checking previous tree N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref $VN.Void N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 d:1 $VN.Void N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 u:1 -- prev tree VN is not related ... checking previous tree N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref $204 N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 d:1 $VN.Void N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref $140 N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this u:1 $80 N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] $100 -- prev tree VN is not related --- Trying RBO in BB01 --- *************** Finishing PHASE Redundant branch opts [no changes] *************** Starting PHASE Optimize Valnum CSEs *************** Finishing PHASE Optimize Valnum CSEs Trees after Optimize Valnum CSEs ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref $204 N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 d:1 $VN.Void N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref $140 N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this u:1 $80 N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] $100 ***** BB01 STMT00002 ( ??? ... 0x007 ) N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref $VN.Void N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 d:1 $VN.Void N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 u:1 ***** BB01 STMT00001 ( ??? ... ??? ) N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null $VN.Null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) N001 ( 0, 0) [000018] ----------- ▌ RETURN void $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) N012 ( 39, 25) [000016] --CXG------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void N011 ( 12, 10) [000028] n--X------- control expr └──▌ IND long N010 ( 10, 8) [000027] ---X---N--- └──▌ ADD long N008 ( 9, 7) [000025] #--X------- ├──▌ IND long N007 ( 7, 5) [000024] ---X---N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #--X------- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 $101 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 $103 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) $81 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Assertion prop GenTreeNode creates assertion: N004 ( 4, 4) [000001] ---XG------ ▌ IND ref In BB01 New Global Constant Assertion: ($80,$0) V00.01 != null, index = #01 GenTreeNode creates assertion: N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void In BB01 New Global Constant Assertion: ($82,$0) V05.01 != null, index = #02 GenTreeNode creates assertion: N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void In BB01 New Global Constant Assertion: ($82,$0) V05.01 == null, index = #03 BB01 valueGen = #01 #03 => BB03 valueGen = #01 #02 BB02 valueGen = #NA BB03 valueGen = #02 BB01: in = #NA out = #01 #03 BB03 = #01 #02 BB02: in = #01 #03 out = #01 #03 BB03: in = #01 #02 out = #01 #02 Propagating #NA for BB01, stmt STMT00000, tree [000000], tree -> #NA Propagating #NA for BB01, stmt STMT00000, tree [000019], tree -> #NA Propagating #NA for BB01, stmt STMT00000, tree [000020], tree -> #NA Propagating #NA for BB01, stmt STMT00000, tree [000001], tree -> #01 Propagating #01 for BB01, stmt STMT00000, tree [000002], tree -> #NA Propagating #01 for BB01, stmt STMT00000, tree [000003], tree -> #NA Propagating #01 for BB01, stmt STMT00002, tree [000004], tree -> #NA Propagating #01 for BB01, stmt STMT00002, tree [000009], tree -> #NA Propagating #01 for BB01, stmt STMT00002, tree [000010], tree -> #NA Propagating #01 for BB01, stmt STMT00001, tree [000005], tree -> #NA Propagating #01 for BB01, stmt STMT00001, tree [000006], tree -> #NA Propagating #01 for BB01, stmt STMT00001, tree [000007], tree -> #NA Propagating #01 for BB01, stmt STMT00001, tree [000008], tree -> #02 Propagating #01 #03 for BB02, stmt STMT00005, tree [000018], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000014], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000013], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000015], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000021], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000022], tree -> #02 VN based non-null prop in BB03: N005 ( 6, 4) [000022] #--X------- ▌ IND long Propagating #01 #02 for BB03, stmt STMT00003, tree [000023], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000024], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000025], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000026], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000027], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000028], tree -> #NA Propagating #01 #02 for BB03, stmt STMT00003, tree [000016], tree -> #NA Re-morphing this stmt: STMT00003 ( ??? ... 0x012 ) N012 ( 39, 25) [000016] --CXG------ ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void N011 ( 12, 10) [000028] n--X------- control expr └──▌ IND long N010 ( 10, 8) [000027] ---X---N--- └──▌ ADD long N008 ( 9, 7) [000025] #--X------- ├──▌ IND long N007 ( 7, 5) [000024] ---X---N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #----O----- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 $101 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 $103 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) $81 ReMorphing args for 16.CALL: Args for [000016].CALL after fgMorphArgs: CallArg[[000013].LCL_VAR ref (By value), 1 reg: rcx, byteAlignment=8, isLate, wellKnown[ThisPointer]] CallArg[[000014].LCL_VAR ref (By value), 1 reg: rdx, byteAlignment=8, isLate] CallArg[[000015].LCL_VAR ref (By value), 1 reg: r8, byteAlignment=8, isLate] OutgoingArgsStackSize is 32 optAssertionPropMain morphed tree: N012 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void N011 ( 12, 10) [000028] n----O----- control expr └──▌ IND long N010 ( 10, 8) [000027] -----O-N--- └──▌ ADD long N008 ( 9, 7) [000025] #----O----- ├──▌ IND long N007 ( 7, 5) [000024] -----O-N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #----O----- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 $101 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 $103 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) $81 *************** Finishing PHASE Assertion prop Trees after Assertion prop ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref $204 N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 d:1 $VN.Void N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref $140 N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this u:1 $80 N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] $100 ***** BB01 STMT00002 ( ??? ... 0x007 ) N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref $VN.Void N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 d:1 $VN.Void N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 u:1 ***** BB01 STMT00001 ( ??? ... ??? ) N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null $VN.Null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) N001 ( 0, 0) [000018] ----------- ▌ RETURN void $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) N012 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void N011 ( 12, 10) [000028] n----O----- control expr └──▌ IND long N010 ( 10, 8) [000027] -----O-N--- └──▌ ADD long N008 ( 9, 7) [000025] #----O----- ├──▌ IND long N007 ( 7, 5) [000024] -----O-N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #----O----- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 $101 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 $103 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) $81 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable *************** Starting PHASE Optimize index checks *************** Finishing PHASE Optimize index checks [no changes] *************** Starting PHASE Insert GC Polls *************** Finishing PHASE Insert GC Polls [no changes] *************** Starting PHASE Optimize bools *************** In optOptimizeBools() optimized 0 BBJ_COND cases, 0 BBJ_RETURN cases in 1 passes *************** Finishing PHASE Optimize bools [no changes] *************** Starting PHASE Optimize layout *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgExpandRarelyRunBlocks() *************** In fgReorderBlocks() Initial BasicBlocks ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** Finishing PHASE Optimize layout Trees after Optimize layout ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i BB02 [0001] 1 BB01 0.50 [009..00B) (return) i BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ***** BB01 STMT00000 ( 0x000[E-] ... 0x007 ) N006 ( 4, 4) [000003] -A-XG---R-- ▌ ASG ref $204 N005 ( 1, 1) [000002] D------N--- ├──▌ LCL_VAR ref V04 tmp1 d:1 $VN.Void N004 ( 4, 4) [000001] ---XG------ └──▌ IND ref N003 ( 2, 2) [000020] -------N--- └──▌ ADD byref $140 N001 ( 1, 1) [000000] ----------- ├──▌ LCL_VAR ref V00 this u:1 $80 N002 ( 1, 1) [000019] ----------- └──▌ CNS_INT long 16 Fseq[_parent] $100 ***** BB01 STMT00002 ( ??? ... 0x007 ) N003 ( 5, 4) [000010] -A------R-- ▌ ASG ref $VN.Void N002 ( 3, 2) [000009] D------N--- ├──▌ LCL_VAR ref V05 tmp2 d:1 $VN.Void N001 ( 1, 1) [000004] ----------- └──▌ LCL_VAR ref V04 tmp1 u:1 ***** BB01 STMT00001 ( ??? ... ??? ) N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void N003 ( 3, 3) [000007] J------N--- └──▌ NE int N001 ( 1, 1) [000005] ----------- ├──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N002 ( 1, 1) [000006] ----------- └──▌ CNS_INT ref null $VN.Null ------------ BB02 [009..00B) (return), preds={BB01} succs={} ***** BB02 STMT00005 ( 0x00A[E-] ... 0x00A ) N001 ( 0, 0) [000018] ----------- ▌ RETURN void $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} ***** BB03 STMT00003 ( ??? ... 0x012 ) N012 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void N011 ( 12, 10) [000028] n----O----- control expr └──▌ IND long N010 ( 10, 8) [000027] -----O-N--- └──▌ ADD long N008 ( 9, 7) [000025] #----O----- ├──▌ IND long N007 ( 7, 5) [000024] -----O-N--- │ └──▌ ADD long N005 ( 6, 4) [000022] #----O----- │ ├──▌ IND long N004 ( 3, 2) [000021] ----------- │ │ └──▌ LCL_VAR ref V05 tmp2 u:1 (last use) N006 ( 1, 1) [000023] ----------- │ └──▌ CNS_INT long 72 $101 N009 ( 1, 1) [000026] ----------- └──▌ CNS_INT long 32 $103 N001 ( 1, 1) [000014] ----------- arg1 in rdx ├──▌ LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- this in rcx ├──▌ LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- arg2 in r8 └──▌ LCL_VAR ref V02 arg2 u:1 (last use) $81 ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Determine first cold block No procedure splitting will be done for this method *************** Finishing PHASE Determine first cold block [no changes] *************** Starting PHASE Rationalize IR rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N006 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 rewriting asg(LCL_VAR, X) to STORE_LCL_VAR(X) N003 ( 5, 4) [000010] DA--------- ▌ STORE_LCL_VAR ref V05 tmp2 d:1 *************** Finishing PHASE Rationalize IR Trees after Rationalize IR ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i LIR BB02 [0001] 1 BB01 0.50 [009..00B) (return) i LIR BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR ref V00 this u:1 $80 N002 ( 1, 1) [000019] ----------- t19 = CNS_INT long 16 Fseq[_parent] $100 ┌──▌ t0 ref ├──▌ t19 long N003 ( 2, 2) [000020] -------N--- t20 = ▌ ADD byref $140 ┌──▌ t20 byref N004 ( 4, 4) [000001] ---XG------ t1 = ▌ IND ref ┌──▌ t1 ref N006 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 N001 ( 1, 1) [000004] ----------- t4 = LCL_VAR ref V04 tmp1 u:1 ┌──▌ t4 ref N003 ( 5, 4) [000010] DA--------- ▌ STORE_LCL_VAR ref V05 tmp2 d:1 N001 ( 1, 1) [000005] ----------- t5 = LCL_VAR ref V05 tmp2 u:1 (last use) N002 ( 1, 1) [000006] ----------- t6 = CNS_INT ref null $VN.Null ┌──▌ t5 ref ├──▌ t6 ref N003 ( 3, 3) [000007] J------N--- t7 = ▌ NE int ┌──▌ t7 int N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void ------------ BB02 [009..00B) (return), preds={BB01} succs={} [000030] ----------- IL_OFFSET void INLRT @ 0x00A[E-] N001 ( 0, 0) [000018] ----------- RETURN void $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} N001 ( 1, 1) [000014] ----------- t14 = LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- t13 = LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- t15 = LCL_VAR ref V02 arg2 u:1 (last use) $81 N004 ( 3, 2) [000021] ----------- t21 = LCL_VAR ref V05 tmp2 u:1 (last use) ┌──▌ t21 ref N005 ( 6, 4) [000022] #----O----- t22 = ▌ IND long N006 ( 1, 1) [000023] ----------- t23 = CNS_INT long 72 $101 ┌──▌ t22 long ├──▌ t23 long N007 ( 7, 5) [000024] -----O-N--- t24 = ▌ ADD long ┌──▌ t24 long N008 ( 9, 7) [000025] #----O----- t25 = ▌ IND long N009 ( 1, 1) [000026] ----------- t26 = CNS_INT long 32 $103 ┌──▌ t25 long ├──▌ t26 long N010 ( 10, 8) [000027] -----O-N--- t27 = ▌ ADD long ┌──▌ t27 long N011 ( 12, 10) [000028] n----O----- t28 = ▌ IND long ┌──▌ t14 ref arg1 in rdx ├──▌ t13 ref this in rcx ├──▌ t15 ref arg2 in r8 ├──▌ t28 long control expr N012 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Do 'simple' lowering outgoingArgSpaceSize not impacted by fast tail call [000016] *************** Finishing PHASE Do 'simple' lowering [no changes] *************** Starting PHASE Lowering nodeinfo Addressing mode: Base N001 ( 1, 1) [000000] ----------- ▌ LCL_VAR ref V00 this u:1 $80 + 16 Removing unused node: N002 ( 1, 1) [000019] -c--------- ▌ CNS_INT long 16 Fseq[_parent] $100 New addressing mode node: N003 ( 2, 2) [000020] ----------- ▌ LEA(b+16) byref lowering store lcl var/field (before): N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR ref V00 this u:1 $80 ┌──▌ t0 ref N003 ( 2, 2) [000020] -c--------- t20 = ▌ LEA(b+16) byref ┌──▌ t20 byref N004 ( 4, 4) [000001] ---XG------ t1 = ▌ IND ref ┌──▌ t1 ref N006 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR ref V00 this u:1 $80 ┌──▌ t0 ref N003 ( 2, 2) [000020] -c--------- t20 = ▌ LEA(b+16) byref ┌──▌ t20 byref N004 ( 4, 4) [000001] ---XG------ t1 = ▌ IND ref ┌──▌ t1 ref N006 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 lowering store lcl var/field (before): N001 ( 1, 1) [000004] ----------- t4 = LCL_VAR ref V04 tmp1 u:1 ┌──▌ t4 ref N003 ( 5, 4) [000010] DA--------- ▌ STORE_LCL_VAR ref V05 tmp2 d:1 lowering store lcl var/field (after): N001 ( 1, 1) [000004] ----------- t4 = LCL_VAR ref V04 tmp1 u:1 ┌──▌ t4 ref N003 ( 5, 4) [000010] DA--------- ▌ STORE_LCL_VAR ref V05 tmp2 d:1 lowering GT_RETURN N001 ( 0, 0) [000018] ----------- ▌ RETURN void $VN.Void ============Addressing mode: Base N005 ( 6, 4) [000022] #----O----- ▌ IND long + 72 Removing unused node: N006 ( 1, 1) [000023] -c--------- ▌ CNS_INT long 72 $101 New addressing mode node: N007 ( 7, 5) [000024] ----------- ▌ LEA(b+72) long Addressing mode: Base N008 ( 9, 7) [000025] #----O----- ▌ IND long + 32 Removing unused node: N009 ( 1, 1) [000026] -c--------- ▌ CNS_INT long 32 $103 New addressing mode node: N010 ( 10, 8) [000027] ----------- ▌ LEA(b+32) long lowering call (before): N001 ( 1, 1) [000014] ----------- t14 = LCL_VAR ref V00 this u:1 (last use) $80 N002 ( 3, 2) [000013] ----------- t13 = LCL_VAR ref V05 tmp2 u:1 N003 ( 3, 2) [000015] ----------- t15 = LCL_VAR ref V02 arg2 u:1 (last use) $81 N004 ( 3, 2) [000021] ----------- t21 = LCL_VAR ref V05 tmp2 u:1 (last use) ┌──▌ t21 ref N005 ( 6, 4) [000022] #----O----- t22 = ▌ IND long ┌──▌ t22 long N007 ( 7, 5) [000024] -c--------- t24 = ▌ LEA(b+72) long ┌──▌ t24 long N008 ( 9, 7) [000025] #----O----- t25 = ▌ IND long ┌──▌ t25 long N010 ( 10, 8) [000027] -c--------- t27 = ▌ LEA(b+32) long ┌──▌ t27 long N011 ( 12, 10) [000028] n----O----- t28 = ▌ IND long ┌──▌ t14 ref arg1 in rdx ├──▌ t13 ref this in rcx ├──▌ t15 ref arg2 in r8 ├──▌ t28 long control expr N012 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void args: ====== late: ====== lowering arg : N001 ( 1, 1) [000014] ----------- ▌ LCL_VAR ref V00 this u:1 (last use) $80 new node is : [000031] ----------- ▌ PUTARG_REG ref REG rdx lowering arg : N002 ( 3, 2) [000013] ----------- ▌ LCL_VAR ref V05 tmp2 u:1 new node is : [000032] ----------- ▌ PUTARG_REG ref REG rcx lowering arg : N003 ( 3, 2) [000015] ----------- ▌ LCL_VAR ref V02 arg2 u:1 (last use) $81 new node is : [000033] ----------- ▌ PUTARG_REG ref REG r8 lowering call (after): N001 ( 1, 1) [000014] ----------- t14 = LCL_VAR ref V00 this u:1 (last use) $80 ┌──▌ t14 ref [000031] ----------- t31 = ▌ PUTARG_REG ref REG rdx N002 ( 3, 2) [000013] ----------- t13 = LCL_VAR ref V05 tmp2 u:1 ┌──▌ t13 ref [000032] ----------- t32 = ▌ PUTARG_REG ref REG rcx N003 ( 3, 2) [000015] ----------- t15 = LCL_VAR ref V02 arg2 u:1 (last use) $81 ┌──▌ t15 ref [000033] ----------- t33 = ▌ PUTARG_REG ref REG r8 N004 ( 3, 2) [000021] ----------- t21 = LCL_VAR ref V05 tmp2 u:1 (last use) ┌──▌ t21 ref N005 ( 6, 4) [000022] #----O----- t22 = ▌ IND long ┌──▌ t22 long N007 ( 7, 5) [000024] -c--------- t24 = ▌ LEA(b+72) long ┌──▌ t24 long N008 ( 9, 7) [000025] #----O----- t25 = ▌ IND long ┌──▌ t25 long N010 ( 10, 8) [000027] -c--------- t27 = ▌ LEA(b+32) long ┌──▌ t27 long N011 ( 12, 10) [000028] nc---O----- t28 = ▌ IND long REG NA ┌──▌ t31 ref arg1 in rdx ├──▌ t32 ref this in rcx ├──▌ t33 ref arg2 in r8 ├──▌ t28 long control expr N012 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void Lower has completed modifying nodes. ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i LIR BB02 [0001] 1 BB01 0.50 [009..00B) (return) i LIR BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR ref V00 this u:1 $80 ┌──▌ t0 ref N003 ( 2, 2) [000020] -c--------- t20 = ▌ LEA(b+16) byref ┌──▌ t20 byref N004 ( 4, 4) [000001] ---XG------ t1 = ▌ IND ref ┌──▌ t1 ref N006 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 N001 ( 1, 1) [000004] ----------- t4 = LCL_VAR ref V04 tmp1 u:1 ┌──▌ t4 ref N003 ( 5, 4) [000010] DA--------- ▌ STORE_LCL_VAR ref V05 tmp2 d:1 N001 ( 1, 1) [000005] ----------- t5 = LCL_VAR ref V05 tmp2 u:1 (last use) N002 ( 1, 1) [000006] -c--------- t6 = CNS_INT ref null $VN.Null ┌──▌ t5 ref ├──▌ t6 ref N003 ( 3, 3) [000007] J------N--- ▌ NE void N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void ------------ BB02 [009..00B) (return), preds={BB01} succs={} [000030] ----------- IL_OFFSET void INLRT @ 0x00A[E-] N001 ( 0, 0) [000018] ----------- RETURN void $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} N001 ( 1, 1) [000014] ----------- t14 = LCL_VAR ref V00 this u:1 (last use) $80 ┌──▌ t14 ref [000031] ----------- t31 = ▌ PUTARG_REG ref REG rdx N002 ( 3, 2) [000013] ----------- t13 = LCL_VAR ref V05 tmp2 u:1 ┌──▌ t13 ref [000032] ----------- t32 = ▌ PUTARG_REG ref REG rcx N003 ( 3, 2) [000015] ----------- t15 = LCL_VAR ref V02 arg2 u:1 (last use) $81 ┌──▌ t15 ref [000033] ----------- t33 = ▌ PUTARG_REG ref REG r8 N004 ( 3, 2) [000021] ----------- t21 = LCL_VAR ref V05 tmp2 u:1 (last use) ┌──▌ t21 ref N005 ( 6, 4) [000022] #----O----- t22 = ▌ IND long ┌──▌ t22 long N007 ( 7, 5) [000024] -c--------- t24 = ▌ LEA(b+72) long ┌──▌ t24 long N008 ( 9, 7) [000025] #----O----- t25 = ▌ IND long ┌──▌ t25 long N010 ( 10, 8) [000027] -c--------- t27 = ▌ LEA(b+32) long ┌──▌ t27 long N011 ( 12, 10) [000028] nc---O----- t28 = ▌ IND long REG NA ┌──▌ t31 ref arg1 in rdx ├──▌ t32 ref this in rcx ├──▌ t33 ref arg2 in r8 ├──▌ t28 long control expr N012 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void ------------------------------------------------------------------------------------------------------------------- *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 1, refCntWtd = 2 New refCnts for V04: refCnt = 2, refCntWtd = 4 New refCnts for V05: refCnt = 1, refCntWtd = 1 New refCnts for V05: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 2, refCntWtd = 1.50 New refCnts for V05: refCnt = 3, refCntWtd = 2.50 New refCnts for V02: refCnt = 1, refCntWtd = 0.50 New refCnts for V05: refCnt = 4, refCntWtd = 3 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 2.50 New refCnts for V00: refCnt = 4, refCntWtd = 3.50 New refCnts for V02: refCnt = 2, refCntWtd = 1.50 New refCnts for V02: refCnt = 3, refCntWtd = 2.50 *************** In fgLocalVarLiveness() ; Initial local variable assignments ; ; V00 this ref this class-hnd single-def ; V01 arg1 int single-def ; V02 arg2 ref class-hnd single-def ; V03 OutArgs lclBlk <0> "OutgoingArgSpace" ; V04 tmp1 ref class-hnd single-def "dup spill" ; V05 tmp2 ref single-def In fgLocalVarLivenessInit Tracked variable (4 out of 6) table: V00 this [ ref]: refCnt = 4, refCntWtd = 3.50 V02 arg2 [ ref]: refCnt = 3, refCntWtd = 2.50 V04 tmp1 [ ref]: refCnt = 2, refCntWtd = 4 V05 tmp2 [ ref]: refCnt = 4, refCntWtd = 3 *************** In fgPerBlockLocalVarLiveness() BB01 USE(1)={V00 } + ByrefExposed + GcHeap DEF(2)={ V04 V05} BB02 USE(0)={} DEF(0)={} BB03 USE(3)={V00 V02 V05} + ByrefExposed + GcHeap DEF(0)={ } + ByrefExposed* + GcHeap* ** Memory liveness computed, GcHeap states and ByrefExposed states match *************** In fgInterBlockLocalVarLiveness() BB liveness after fgLiveVarAnalysis(): BB01 IN (2)={V00 V02 } + ByrefExposed + GcHeap OUT(3)={V00 V02 V05} + ByrefExposed + GcHeap BB02 IN (0)={} OUT(0)={} BB03 IN (3)={V00 V02 V05} + ByrefExposed + GcHeap OUT(0)={ } *************** In fgUpdateFlowGraph() Before updating the flow graph: ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i LIR BB02 [0001] 1 BB01 0.50 [009..00B) (return) i LIR BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgRemoveDeadBlocks() Removing unreachable blocks for fgRemoveDeadBlocks iteration #1 *************** In fgDebugCheckBBlist *** lvaComputeRefCounts *** *** lvaComputeRefCounts -- explicit counts *** New refCnts for V00: refCnt = 1, refCntWtd = 1 New refCnts for V04: refCnt = 1, refCntWtd = 2 New refCnts for V04: refCnt = 2, refCntWtd = 4 New refCnts for V05: refCnt = 1, refCntWtd = 1 New refCnts for V05: refCnt = 2, refCntWtd = 2 New refCnts for V00: refCnt = 2, refCntWtd = 1.50 New refCnts for V05: refCnt = 3, refCntWtd = 2.50 New refCnts for V02: refCnt = 1, refCntWtd = 0.50 New refCnts for V05: refCnt = 4, refCntWtd = 3 *** lvaComputeRefCounts -- implicit counts *** New refCnts for V00: refCnt = 3, refCntWtd = 2.50 New refCnts for V00: refCnt = 4, refCntWtd = 3.50 New refCnts for V02: refCnt = 2, refCntWtd = 1.50 New refCnts for V02: refCnt = 3, refCntWtd = 2.50 *************** Finishing PHASE Lowering nodeinfo Trees after Lowering nodeinfo ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i LIR BB02 [0001] 1 BB01 0.50 [009..00B) (return) i LIR BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] N001 ( 1, 1) [000000] ----------- t0 = LCL_VAR ref V00 this u:1 $80 ┌──▌ t0 ref N003 ( 2, 2) [000020] -c--------- t20 = ▌ LEA(b+16) byref ┌──▌ t20 byref N004 ( 4, 4) [000001] ---XG------ t1 = ▌ IND ref ┌──▌ t1 ref N006 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 N001 ( 1, 1) [000004] ----------- t4 = LCL_VAR ref V04 tmp1 u:1 (last use) ┌──▌ t4 ref N003 ( 5, 4) [000010] DA--------- ▌ STORE_LCL_VAR ref V05 tmp2 d:1 N001 ( 1, 1) [000005] ----------- t5 = LCL_VAR ref V05 tmp2 u:1 N002 ( 1, 1) [000006] -c--------- t6 = CNS_INT ref null $VN.Null ┌──▌ t5 ref ├──▌ t6 ref N003 ( 3, 3) [000007] J------N--- ▌ NE void N004 ( 5, 5) [000008] ----------- ▌ JTRUE void $VN.Void ------------ BB02 [009..00B) (return), preds={BB01} succs={} [000030] ----------- IL_OFFSET void INLRT @ 0x00A[E-] N001 ( 0, 0) [000018] ----------- RETURN void $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} N001 ( 1, 1) [000014] ----------- t14 = LCL_VAR ref V00 this u:1 (last use) $80 ┌──▌ t14 ref [000031] ----------- t31 = ▌ PUTARG_REG ref REG rdx N002 ( 3, 2) [000013] ----------- t13 = LCL_VAR ref V05 tmp2 u:1 ┌──▌ t13 ref [000032] ----------- t32 = ▌ PUTARG_REG ref REG rcx N003 ( 3, 2) [000015] ----------- t15 = LCL_VAR ref V02 arg2 u:1 (last use) $81 ┌──▌ t15 ref [000033] ----------- t33 = ▌ PUTARG_REG ref REG r8 N004 ( 3, 2) [000021] ----------- t21 = LCL_VAR ref V05 tmp2 u:1 (last use) ┌──▌ t21 ref N005 ( 6, 4) [000022] #----O----- t22 = ▌ IND long ┌──▌ t22 long N007 ( 7, 5) [000024] -c--------- t24 = ▌ LEA(b+72) long ┌──▌ t24 long N008 ( 9, 7) [000025] #----O----- t25 = ▌ IND long ┌──▌ t25 long N010 ( 10, 8) [000027] -c--------- t27 = ▌ LEA(b+32) long ┌──▌ t27 long N011 ( 12, 10) [000028] nc---O----- t28 = ▌ IND long REG NA ┌──▌ t31 ref arg1 in rdx ├──▌ t32 ref this in rcx ├──▌ t33 ref arg2 in r8 ├──▌ t28 long control expr N012 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Calculate stack level slots *************** Finishing PHASE Calculate stack level slots [no changes] *************** Starting PHASE Linear scan register alloc Clearing modified regs. buildIntervals ======== ----------------- LIVENESS: ----------------- BB01 use: {V00} def: {V04 V05} in: {V00 V02} out: {V00 V02 V05} BB02 use: {} def: {} in: {} out: {} BB03 use: {V00 V02 V05} def: {} in: {V00 V02 V05} out: {} Interval 0: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 0: (V00) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 1: (V02) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 2: (V04) ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: ref RefPositions {} physReg:NA Preferences=[allInt] Interval 3: (V05) ref RefPositions {} physReg:NA Preferences=[allInt] FP callee save candidate vars: None floatVarCount = 0; hasLoops = false, singleExit = false TUPLE STYLE DUMP BEFORE LSRA Start LSRA Block Sequence: Current block: BB01 Succ block: BB02, Criteria: weight, Worklist: [BB02 ] Succ block: BB03, Criteria: bbNum, Worklist: [BB02 BB03 ] Current block: BB02 Current block: BB03 Final LSRA Block Sequence: BB01 ( 1 ) BB02 ( 0.50) BB03 ( 0.50) BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ===== N000. IL_OFFSET INLRT @ 0x000[E-] N001. V00(t0) N003. t20 = LEA(b+16); t0 N004. t1 = IND ; t20 N006. V04(t3); t1 N001. V04(t4*) N003. V05(t10); t4* N001. V05(t5) N002. CNS_INT null N003. NE ; t5 N004. JTRUE BB02 [009..00B) (return), preds={BB01} succs={} ===== N000. IL_OFFSET INLRT @ 0x00A[E-] N001. RETURN BB03 [00B..013) (return), preds={BB01} succs={} ===== N001. V00(t14*) N000. t31 = PUTARG_REG; t14* N002. V05(t13) N000. t32 = PUTARG_REG; t13 N003. V02(t15*) N000. t33 = PUTARG_REG; t15* N004. V05(t21*) N005. t22 = IND ; t21* N007. t24 = LEA(b+72); t22 N008. t25 = IND ; t24 N010. t27 = LEA(b+32); t25 N011. t28 = IND ; t27 N012. CALLV vt-ind; t31,t32,t33,t28 buildIntervals second part ======== Int arg V00 in reg rcx BB00 regmask=[rcx] minReg=1 fixed wt=100.00> Int arg V02 in reg r8 BB00 regmask=[r8] minReg=1 fixed wt=100.00> Int arg V01 in reg rdx NEW BLOCK BB01 DefList: { } N003 (???,???) [000029] ----------- ▌ IL_OFFSET void INLRT @ 0x000[E-] REG NA DefList: { } N005 ( 1, 1) [000000] ----------- ▌ LCL_VAR ref V00 this u:1 NA REG NA $80 DefList: { } N007 ( 2, 2) [000020] -c--------- ▌ LEA(b+16) byref REG NA Contained DefList: { } N009 ( 4, 4) [000001] ---XG------ ▌ IND ref REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=350.00> Interval 4: ref RefPositions {} physReg:NA Preferences=[allInt] IND BB01 regmask=[allInt] minReg=1 wt=400.00> DefList: { N009.t1. IND } N011 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 NA REG NA BB01 regmask=[allInt] minReg=1 last wt=100.00> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00> DefList: { } N013 ( 1, 1) [000004] ----------- ▌ LCL_VAR ref V04 tmp1 u:1 NA (last use) REG NA DefList: { } N015 ( 5, 4) [000010] DA--------- ▌ STORE_LCL_VAR ref V05 tmp2 d:1 NA REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00> Assigning related to STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00> DefList: { } N017 ( 1, 1) [000005] ----------- ▌ LCL_VAR ref V05 tmp2 u:1 NA REG NA DefList: { } N019 ( 1, 1) [000006] -c--------- ▌ CNS_INT ref null REG NA $VN.Null Contained DefList: { } N021 ( 3, 3) [000007] J------N--- ▌ NE void REG NA LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=300.00> DefList: { } N023 ( 5, 5) [000008] ----------- ▌ JTRUE void REG NA $VN.Void CHECKING LAST USES for BB01, liveout={V00 V02 V05} ============================== use: {V00} def: {V04 V05} NEW BLOCK BB02 Setting BB01 as the predecessor for determining incoming variable registers of BB02 DefList: { } N027 (???,???) [000030] ----------- ▌ IL_OFFSET void INLRT @ 0x00A[E-] REG NA DefList: { } N029 ( 0, 0) [000018] ----------- ▌ RETURN void REG NA $VN.Void CHECKING LAST USES for BB02, liveout={} ============================== use: {} def: {} NEW BLOCK BB03 Setting BB01 as the predecessor for determining incoming variable registers of BB03 DefList: { } N033 ( 1, 1) [000014] ----------- ▌ LCL_VAR ref V00 this u:1 NA (last use) REG NA $80 DefList: { } N035 (???,???) [000031] ----------- ▌ PUTARG_REG ref REG rdx BB03 regmask=[rdx] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=350.00> Interval 5: ref RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rdx] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=200.00> DefList: { N035.t31. PUTARG_REG } N037 ( 3, 2) [000013] ----------- ▌ LCL_VAR ref V05 tmp2 u:1 NA REG NA DefList: { N035.t31. PUTARG_REG } N039 (???,???) [000032] ----------- ▌ PUTARG_REG ref REG rcx BB03 regmask=[rcx] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[rcx] minReg=1 last fixed wt=300.00> Setting putarg_reg as a pass-through of a non-last use lclVar Interval 6: ref RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[rcx] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=200.00> Assigning related to DefList: { N035.t31. PUTARG_REG; N039.t32. PUTARG_REG } N041 ( 3, 2) [000015] ----------- ▌ LCL_VAR ref V02 arg2 u:1 NA (last use) REG NA $81 DefList: { N035.t31. PUTARG_REG; N039.t32. PUTARG_REG } N043 (???,???) [000033] ----------- ▌ PUTARG_REG ref REG r8 Last use of V02 between PUTARG and CALL. Removing occupied arg regs from preferences: [rcx rdx] BB03 regmask=[r8] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[r8] minReg=1 last fixed wt=250.00> Interval 7: ref RefPositions {} physReg:NA Preferences=[allInt] BB03 regmask=[r8] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[r8] minReg=1 fixed wt=200.00> DefList: { N035.t31. PUTARG_REG; N039.t32. PUTARG_REG; N043.t33. PUTARG_REG } N045 ( 3, 2) [000021] ----------- ▌ LCL_VAR ref V05 tmp2 u:1 NA (last use) REG NA DefList: { N035.t31. PUTARG_REG; N039.t32. PUTARG_REG; N043.t33. PUTARG_REG } N047 ( 6, 4) [000022] #----O----- ▌ IND long REG NA Last use of V05 between PUTARG and CALL. Removing occupied arg regs from preferences: [rdx r8] LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=300.00> Interval 8: long RefPositions {} physReg:NA Preferences=[allInt] IND BB03 regmask=[allInt] minReg=1 wt=200.00> DefList: { N035.t31. PUTARG_REG; N039.t32. PUTARG_REG; N043.t33. PUTARG_REG; N047.t22. IND } N049 ( 7, 5) [000024] -c--------- ▌ LEA(b+72) long REG NA Contained DefList: { N035.t31. PUTARG_REG; N039.t32. PUTARG_REG; N043.t33. PUTARG_REG; N047.t22. IND } N051 ( 9, 7) [000025] #----O----- ▌ IND long REG NA BB03 regmask=[allInt] minReg=1 last wt=50.00> Interval 9: long RefPositions {} physReg:NA Preferences=[allInt] IND BB03 regmask=[allInt] minReg=1 wt=200.00> DefList: { N035.t31. PUTARG_REG; N039.t32. PUTARG_REG; N043.t33. PUTARG_REG; N051.t25. IND } N053 ( 10, 8) [000027] -c--------- ▌ LEA(b+32) long REG NA Contained DefList: { N035.t31. PUTARG_REG; N039.t32. PUTARG_REG; N043.t33. PUTARG_REG; N051.t25. IND } N055 ( 12, 10) [000028] nc---O----- ▌ IND long REG NA Contained DefList: { N035.t31. PUTARG_REG; N039.t32. PUTARG_REG; N043.t33. PUTARG_REG; N051.t25. IND } N057 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName REG NA $VN.Void BB03 regmask=[rdx] minReg=1 wt=50.00> BB03 regmask=[rdx] minReg=1 last fixed wt=50.00> BB03 regmask=[rcx] minReg=1 wt=50.00> BB03 regmask=[rcx] minReg=1 last fixed wt=50.00> BB03 regmask=[r8] minReg=1 wt=50.00> BB03 regmask=[r8] minReg=1 last fixed wt=50.00> BB03 regmask=[rax rcx rdx r8-r11] minReg=1 last wt=50.00> BB03 regmask=[rax] minReg=1 wt=50.00> BB03 regmask=[rcx] minReg=1 wt=50.00> BB03 regmask=[rdx] minReg=1 wt=50.00> BB03 regmask=[r8] minReg=1 wt=50.00> BB03 regmask=[r9] minReg=1 wt=50.00> BB03 regmask=[r10] minReg=1 wt=50.00> BB03 regmask=[r11] minReg=1 wt=50.00> CHECKING LAST USES for BB03, liveout={} ============================== use: {V00 V02 V05} def: {} Linear scan intervals BEFORE VALIDATING INTERVALS: Interval 0: (V00) ref RefPositions {#0@0 #3@9 #13@35} physReg:rcx Preferences=[rcx rdx] Interval 1: (V02) ref RefPositions {#1@0 #21@43} physReg:r8 Preferences=[r8] Interval 2: (V04) ref RefPositions {#6@12 #7@15} physReg:NA Preferences=[allInt] RelatedInterval Interval 3: (V05) ref RefPositions {#8@16 #9@21 #17@39 #24@47} physReg:NA Preferences=[rcx] Interval 4: ref RefPositions {#4@10 #5@11} physReg:NA Preferences=[allInt] RelatedInterval Interval 5: ref RefPositions {#15@36 #29@57} physReg:NA Preferences=[rdx] Interval 6: ref (specialPutArg) RefPositions {#19@40 #31@57} physReg:NA Preferences=[rcx] RelatedInterval Interval 7: ref RefPositions {#23@44 #33@57} physReg:NA Preferences=[r8] Interval 8: long RefPositions {#25@48 #26@51} physReg:NA Preferences=[allInt] Interval 9: long RefPositions {#27@52 #34@57} physReg:NA Preferences=[rax rcx rdx r8-r11] ------------ REFPOSITIONS BEFORE VALIDATING INTERVALS: ------------ BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=350.00> IND BB01 regmask=[allInt] minReg=1 wt=400.00> BB01 regmask=[allInt] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=300.00> BB03 regmask=[rdx] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=350.00> BB03 regmask=[rdx] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=200.00> BB03 regmask=[rcx] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed wt=300.00> BB03 regmask=[rcx] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=200.00> BB03 regmask=[r8] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[r8] minReg=1 last fixed wt=250.00> BB03 regmask=[r8] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[r8] minReg=1 fixed wt=200.00> LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=300.00> IND BB03 regmask=[allInt] minReg=1 wt=200.00> BB03 regmask=[allInt] minReg=1 last wt=50.00> IND BB03 regmask=[rax rcx rdx r8-r11] minReg=1 wt=200.00> BB03 regmask=[rdx] minReg=1 wt=50.00> BB03 regmask=[rdx] minReg=1 last fixed wt=50.00> BB03 regmask=[rcx] minReg=1 wt=50.00> BB03 regmask=[rcx] minReg=1 last fixed wt=50.00> BB03 regmask=[r8] minReg=1 wt=50.00> BB03 regmask=[r8] minReg=1 last fixed wt=50.00> BB03 regmask=[rax rcx rdx r8-r11] minReg=1 last wt=50.00> BB03 regmask=[rax] minReg=1 last wt=50.00> BB03 regmask=[rcx] minReg=1 last wt=50.00> BB03 regmask=[rdx] minReg=1 last wt=50.00> BB03 regmask=[r8] minReg=1 last wt=50.00> BB03 regmask=[r9] minReg=1 last wt=50.00> BB03 regmask=[r10] minReg=1 last wt=50.00> BB03 regmask=[r11] minReg=1 last wt=50.00> ------------ REFPOSITIONS DURING VALIDATE INTERVALS (RefPositions per interval) ------------ ----------------- BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=350.00> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=350.00> ----------------- BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB03 regmask=[r8] minReg=1 last fixed wt=250.00> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00> ----------------- STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=300.00> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed wt=300.00> LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=300.00> TUPLE STYLE DUMP WITH REF POSITIONS Incoming Parameters: V00 V02 BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ===== N003. IL_OFFSET INLRT @ 0x000[E-] N005. V00(L0) N007. LEA(b+16) N009. IND Use:(#3) Def:(#4) Pref: N011. V04(L2) Use:(#5) * Def:(#6) Pref: N013. V04(L2) N015. V05(L3) Use:(#7) * Def:(#8) N017. V05(L3) N019. CNS_INT null N021. NE Use:(#9) N023. JTRUE BB02 [009..00B) (return), preds={BB01} succs={} ===== N027. IL_OFFSET INLRT @ 0x00A[E-] N029. RETURN BB03 [00B..013) (return), preds={BB01} succs={} ===== N033. V00(L0) N035. PUTARG_REG Use:(#13) Fixed:rdx(#12) * Def:(#15) rdx N037. V05(L3) N039. PUTARG_REG Use:(#17) Fixed:rcx(#16) Def:(#19) rcx Pref: N041. V02(L1) N043. PUTARG_REG Use:(#21) Fixed:r8(#20) * Def:(#23) r8 N045. V05(L3) N047. IND Use:(#24) * Def:(#25) N049. LEA(b+72) N051. IND Use:(#26) * Def:(#27) N053. LEA(b+32) N055. IND N057. CALLV vt-ind Use:(#29) Fixed:rdx(#28) * Use:(#31) Fixed:rcx(#30) * Use:(#33) Fixed:r8(#32) * Use:(#34) * Kill: rax rcx rdx r8 r9 r10 r11 Linear scan intervals after buildIntervals: Interval 0: (V00) ref RefPositions {#0@0 #3@9 #13@35} physReg:rcx Preferences=[rcx rdx] Interval 1: (V02) ref RefPositions {#1@0 #21@43} physReg:r8 Preferences=[r8] Interval 2: (V04) ref RefPositions {#6@12 #7@15} physReg:NA Preferences=[allInt] RelatedInterval Interval 3: (V05) ref RefPositions {#8@16 #9@21 #17@39 #24@47} physReg:NA Preferences=[rcx] Interval 4: ref RefPositions {#4@10 #5@11} physReg:NA Preferences=[allInt] RelatedInterval Interval 5: ref RefPositions {#15@36 #29@57} physReg:NA Preferences=[rdx] Interval 6: ref (specialPutArg) RefPositions {#19@40 #31@57} physReg:NA Preferences=[rcx] RelatedInterval Interval 7: ref RefPositions {#23@44 #33@57} physReg:NA Preferences=[r8] Interval 8: long RefPositions {#25@48 #26@51} physReg:NA Preferences=[allInt] Interval 9: long RefPositions {#27@52 #34@57} physReg:NA Preferences=[rax rcx rdx r8-r11] *************** In LinearScan::allocateRegisters() Linear scan intervals before allocateRegisters: Interval 0: (V00) ref RefPositions {#0@0 #3@9 #13@35} physReg:rcx Preferences=[rcx rdx] Interval 1: (V02) ref RefPositions {#1@0 #21@43} physReg:r8 Preferences=[r8] Interval 2: (V04) ref RefPositions {#6@12 #7@15} physReg:NA Preferences=[allInt] RelatedInterval Interval 3: (V05) ref RefPositions {#8@16 #9@21 #17@39 #24@47} physReg:NA Preferences=[rcx] Interval 4: ref RefPositions {#4@10 #5@11} physReg:NA Preferences=[allInt] RelatedInterval Interval 5: ref RefPositions {#15@36 #29@57} physReg:NA Preferences=[rdx] Interval 6: ref (specialPutArg) RefPositions {#19@40 #31@57} physReg:NA Preferences=[rcx] RelatedInterval Interval 7: ref RefPositions {#23@44 #33@57} physReg:NA Preferences=[r8] Interval 8: long RefPositions {#25@48 #26@51} physReg:NA Preferences=[allInt] Interval 9: long RefPositions {#27@52 #34@57} physReg:NA Preferences=[rax rcx rdx r8-r11] ------------ REFPOSITIONS BEFORE ALLOCATION: ------------ BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=350.00> IND BB01 regmask=[allInt] minReg=1 wt=400.00> BB01 regmask=[allInt] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00> STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=300.00> BB03 regmask=[rdx] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=350.00> BB03 regmask=[rdx] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=200.00> BB03 regmask=[rcx] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed wt=300.00> BB03 regmask=[rcx] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=200.00> BB03 regmask=[r8] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[r8] minReg=1 last fixed wt=250.00> BB03 regmask=[r8] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[r8] minReg=1 fixed wt=200.00> LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=300.00> IND BB03 regmask=[allInt] minReg=1 wt=200.00> BB03 regmask=[allInt] minReg=1 last wt=50.00> IND BB03 regmask=[rax rcx rdx r8-r11] minReg=1 wt=200.00> BB03 regmask=[rdx] minReg=1 wt=50.00> BB03 regmask=[rdx] minReg=1 last fixed wt=50.00> BB03 regmask=[rcx] minReg=1 wt=50.00> BB03 regmask=[rcx] minReg=1 last fixed wt=50.00> BB03 regmask=[r8] minReg=1 wt=50.00> BB03 regmask=[r8] minReg=1 last fixed wt=50.00> BB03 regmask=[rax rcx rdx r8-r11] minReg=1 last wt=50.00> BB03 regmask=[rax] minReg=1 last wt=50.00> BB03 regmask=[rcx] minReg=1 last wt=50.00> BB03 regmask=[rdx] minReg=1 last wt=50.00> BB03 regmask=[r8] minReg=1 last wt=50.00> BB03 regmask=[r9] minReg=1 last wt=50.00> BB03 regmask=[r10] minReg=1 last wt=50.00> BB03 regmask=[r11] minReg=1 last wt=50.00> VAR REFPOSITIONS BEFORE ALLOCATION --- V00 (Interval 0) BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[allInt] minReg=1 wt=350.00> LCL_VAR BB03 regmask=[rdx] minReg=1 last fixed wt=350.00> --- V01 --- V02 (Interval 1) BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB03 regmask=[r8] minReg=1 last fixed wt=250.00> --- V03 --- V04 (Interval 2) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[allInt] minReg=1 last wt=400.00> --- V05 (Interval 3) STORE_LCL_VAR BB01 regmask=[allInt] minReg=1 wt=300.00> LCL_VAR BB01 regmask=[allInt] minReg=1 regOptional wt=300.00> LCL_VAR BB03 regmask=[rcx] minReg=1 fixed wt=300.00> LCL_VAR BB03 regmask=[allInt] minReg=1 last wt=300.00> Allocating Registers -------------------- The following table has one or more rows for each RefPosition that is handled during allocation. The columns are: (1) Loc: LSRA location, (2) RP#: RefPosition number, (3) Name, (4) Type (e.g. Def, Use, Fixd, Parm, DDef (Dummy Def), ExpU (Exposed Use), Kill) followed by a '*' if it is a last use, and a 'D' if it is delayRegFree, (5) Action taken during allocation. Some actions include (a) Alloc a new register, (b) Keep an existing register, (c) Spill a register, (d) ReLod (Reload) a register. If an ALL-CAPS name such as COVRS is displayed, it is a score name from lsra_score.h, with a trailing '(A)' indicating alloc, '(C)' indicating copy, and '(R)' indicating re-use. See dumpLsraAllocationEvent() for details. The subsequent columns show the Interval occupying each register, if any, followed by 'a' if it is active, 'p' if it is a large vector that has been partially spilled, and 'i' if it is inactive. Columns are only printed up to the last modified register, which may increase during allocation, in which case additional columns will appear. Registers which are not marked modified have ---- in their column. ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ TreeID LocRP# Name Type Action Reg │rax │rcx │rdx │rbx │rbp │rsi │rdi │r8 │r9 │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ │ │V0 a│ │ │ │ │ │V2 a│ │ 0.#0 V0 Parm Keep rcx │ │V0 a│ │ │ │ │ │V2 a│ │ 0.#1 V2 Parm Keep r8 │ │V0 a│ │ │ │ │ │V2 a│ │ 1.#2 BB1 PredBB0 │ │V0 a│ │ │ │ │ │V2 a│ │ [000001] 9.#3 V0 Use Keep rcx │ │V0 a│ │ │ │ │ │V2 a│ │ 10.#4 I4 Def BSFIT(A) rdx │ │V0 a│I4 a│ │ │ │ │V2 a│ │ [000003] 11.#5 I4 Use * Keep rdx │ │V0 a│I4 a│ │ │ │ │V2 a│ │ 12.#6 V4 Def COVRS(A) rdx │ │V0 a│V4 a│ │ │ │ │V2 a│ │ [000010] 15.#7 V4 Use * Keep rdx │ │V0 a│V4 a│ │ │ │ │V2 a│ │ 16.#8 V5 Def COVRS(A) rdx │ │V0 a│V5 a│ │ │ │ │V2 a│ │ [000007] 21.#9 V5 Use Keep rdx │ │V0 a│V5 a│ │ │ │ │V2 a│ │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ TreeID LocRP# Name Type Action Reg │rax │rcx │rdx │rbx │rbp │rsi │rdi │r8 │r9 │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ 25.#10 BB2 PredBB1 │ │V0 i│V5 i│ │ │ │ │V2 i│ │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ TreeID LocRP# Name Type Action Reg │rax │rcx │rdx │rbx │rbp │rsi │rdi │r8 │r9 │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ 31.#11 BB3 PredBB1 │ │V0 a│V5 a│ │ │ │ │V2 a│ │ [000031] 35.#12 rdx Fixd Keep rdx │ │V0 a│V5 a│ │ │ │ │V2 a│ │ 35.#13 V0 Use * Spill rdx │ │V0 i│ │ │ │ │ │V2 a│ │ Copy rdx │ │V0 a│V0 a│ │ │ │ │V2 a│ │ 36.#14 rdx Fixd Keep rdx │ │ │ │ │ │ │ │V2 a│ │ 36.#15 I5 Def Alloc rdx │ │ │I5 a│ │ │ │ │V2 a│ │ [000032] 39.#16 rcx Fixd Keep rcx │ │ │I5 a│ │ │ │ │V2 a│ │ 39.#17 V5 Use ReLod NA │ │ │I5 a│ │ │ │ │V2 a│ │ Alloc rcx │ │V5 a│I5 a│ │ │ │ │V2 a│ │ 40.#18 rcx Fixd Keep rcx │ │V5 a│I5 a│ │ │ │ │V2 a│ │ 40.#19 I6 Def PtArg rcx │ │V5 a│I5 a│ │ │ │ │V2 a│ │ [000033] 43.#20 r8 Fixd Keep r8 │ │V5 a│I5 a│ │ │ │ │V2 a│ │ 43.#21 V2 Use * Keep r8 │ │V5 a│I5 a│ │ │ │ │V2 a│ │ 44.#22 r8 Fixd Keep r8 │ │V5 a│I5 a│ │ │ │ │ │ │ 44.#23 I7 Def Alloc r8 │ │V5 a│I5 a│ │ │ │ │I7 a│ │ [000022] 47.#24 V5 Use * Keep rcx │ │V5 a│I5 a│ │ │ │ │I7 a│ │ 48.#25 I8 Def ORDER(A) rax │I8 a│Busy│I5 a│ │ │ │ │I7 a│ │ [000025] 51.#26 I8 Use * Keep rax │I8 a│Busy│I5 a│ │ │ │ │I7 a│ │ 52.#27 I9 Def ORDER(A) rax │I9 a│Busy│I5 a│ │ │ │ │I7 a│ │ [000016] 57.#28 rdx Fixd Keep rdx │I9 a│Busy│I5 a│ │ │ │ │I7 a│ │ 57.#29 I5 Use * Keep rdx │I9 a│Busy│I5 a│ │ │ │ │I7 a│ │ 57.#30 rcx Fixd Keep rcx │I9 a│Busy│I5 a│ │ │ │ │I7 a│ │ 57.#31 I6 Use * PtArg rcx │I9 a│Busy│I5 a│ │ │ │ │I7 a│ │ 57.#32 r8 Fixd Keep r8 │I9 a│Busy│I5 a│ │ │ │ │I7 a│ │ 57.#33 I7 Use * Keep r8 │I9 a│Busy│I5 a│ │ │ │ │I7 a│ │ 57.#34 I9 Use * Keep rax │I9 a│Busy│I5 a│ │ │ │ │I7 a│ │ 58.#35 rax Kill Keep rax │ │Busy│ │ │ │ │ │ │ │ 58.#36 rcx Kill Keep rcx │ │ │ │ │ │ │ │ │ │ 58.#37 rdx Kill Keep rdx │ │ │ │ │ │ │ │ │ │ 58.#38 r8 Kill Keep r8 │ │ │ │ │ │ │ │ │ │ 58.#39 r9 Kill Keep r9 │ │ │ │ │ │ │ │ │ │ 58.#40 r10 Kill Keep r10 │ │ │ │ │ │ │ │ │ │ 58.#41 r11 Kill Keep r11 │ │ │ │ │ │ │ │ │ │ ------------ REFPOSITIONS AFTER ALLOCATION: ------------ BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00> BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=350.00> IND BB01 regmask=[rdx] minReg=1 wt=400.00> BB01 regmask=[rdx] minReg=1 last wt=100.00> STORE_LCL_VAR BB01 regmask=[rdx] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[rdx] minReg=1 last wt=400.00> STORE_LCL_VAR BB01 regmask=[rdx] minReg=1 singleDefSpill wt=150.00> LCL_VAR BB01 regmask=[rdx] minReg=1 spillAfter regOptional wt=150.00> BB03 regmask=[rdx] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[rdx] minReg=1 last copy fixed wt=350.00> BB03 regmask=[rdx] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[rdx] minReg=1 fixed wt=200.00> BB03 regmask=[rcx] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[rcx] minReg=1 reload fixed wt=150.00> BB03 regmask=[rcx] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[rcx] minReg=1 fixed wt=200.00> BB03 regmask=[r8] minReg=1 wt=50.00> LCL_VAR BB03 regmask=[r8] minReg=1 last fixed wt=250.00> BB03 regmask=[r8] minReg=1 wt=50.00> PUTARG_REG BB03 regmask=[r8] minReg=1 fixed wt=200.00> LCL_VAR BB03 regmask=[rcx] minReg=1 last wt=150.00> IND BB03 regmask=[rax] minReg=1 wt=200.00> BB03 regmask=[rax] minReg=1 last wt=50.00> IND BB03 regmask=[rax] minReg=1 wt=200.00> BB03 regmask=[rdx] minReg=1 wt=50.00> BB03 regmask=[rdx] minReg=1 last fixed wt=50.00> BB03 regmask=[rcx] minReg=1 wt=50.00> BB03 regmask=[rcx] minReg=1 last fixed wt=50.00> BB03 regmask=[r8] minReg=1 wt=50.00> BB03 regmask=[r8] minReg=1 last fixed wt=50.00> BB03 regmask=[rax] minReg=1 last wt=50.00> BB03 regmask=[rax] minReg=1 last wt=50.00> BB03 regmask=[rcx] minReg=1 last wt=50.00> BB03 regmask=[rdx] minReg=1 last wt=50.00> BB03 regmask=[r8] minReg=1 last wt=50.00> BB03 regmask=[r9] minReg=1 last wt=50.00> BB03 regmask=[r10] minReg=1 last wt=50.00> BB03 regmask=[r11] minReg=1 last wt=50.00> VAR REFPOSITIONS AFTER ALLOCATION --- V00 (Interval 0) BB00 regmask=[rcx] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB01 regmask=[rcx] minReg=1 wt=350.00> LCL_VAR BB03 regmask=[rdx] minReg=1 last copy fixed wt=350.00> --- V01 --- V02 (Interval 1) BB00 regmask=[r8] minReg=1 fixed regOptional wt=100.00> LCL_VAR BB03 regmask=[r8] minReg=1 last fixed wt=250.00> --- V03 --- V04 (Interval 2) STORE_LCL_VAR BB01 regmask=[rdx] minReg=1 wt=400.00> LCL_VAR BB01 regmask=[rdx] minReg=1 last wt=400.00> --- V05 (Interval 3) STORE_LCL_VAR BB01 regmask=[rdx] minReg=1 singleDefSpill wt=150.00> LCL_VAR BB01 regmask=[rdx] minReg=1 spillAfter regOptional wt=150.00> LCL_VAR BB03 regmask=[rcx] minReg=1 reload fixed wt=150.00> LCL_VAR BB03 regmask=[rcx] minReg=1 last wt=150.00> Active intervals at end of allocation: ----------------------- RESOLVING BB BOUNDARIES ----------------------- Resolution Candidates: {V00 V02 V05} Has No Critical Edges Prior to Resolution BB01 use: {V00} def: {V04 V05} in: {V00 V02} out: {V00 V02 V05} Var=Reg beg of BB01: V00=rcx V02=r8 Var=Reg end of BB01: V00=rcx V02=r8 BB02 use: {} def: {} in: {} out: {} Var=Reg beg of BB02: none Var=Reg end of BB02: none BB03 use: {V00 V02 V05} def: {} in: {V00 V02 V05} out: {} Var=Reg beg of BB03: V00=rcx V02=r8 Var=Reg end of BB03: none RESOLVING EDGES Set V00 argument initial register to rcx Set V02 argument initial register to r8 Trees after linear scan register allocator (LSRA) ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i LIR BB02 [0001] 1 BB01 0.50 [009..00B) (return) i LIR BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} N003 (???,???) [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR ref V00 this u:1 rcx REG rcx $80 ┌──▌ t0 ref N007 ( 2, 2) [000020] -c--------- t20 = ▌ LEA(b+16) byref REG NA ┌──▌ t20 byref N009 ( 4, 4) [000001] ---XG------ t1 = ▌ IND ref REG rdx ┌──▌ t1 ref N011 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 rdx REG rdx N013 ( 1, 1) [000004] ----------- t4 = LCL_VAR ref V04 tmp1 u:1 rdx (last use) REG rdx ┌──▌ t4 ref N015 ( 5, 4) [000010] DA--------z ▌ STORE_LCL_VAR ref V05 tmp2 d:1 rdx REG rdx N017 ( 1, 1) [000005] ----------Z t5 = LCL_VAR ref V05 tmp2 u:1 rdx REG rdx N019 ( 1, 1) [000006] -c--------- t6 = CNS_INT ref null REG NA $VN.Null ┌──▌ t5 ref ├──▌ t6 ref N021 ( 3, 3) [000007] J------N--- ▌ NE void REG NA N023 ( 5, 5) [000008] ----------- ▌ JTRUE void REG NA $VN.Void ------------ BB02 [009..00B) (return), preds={BB01} succs={} N027 (???,???) [000030] ----------- IL_OFFSET void INLRT @ 0x00A[E-] REG NA N029 ( 0, 0) [000018] ----------- RETURN void REG NA $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} N033 ( 1, 1) [000014] ----------- t14 = LCL_VAR ref V00 this u:1 rcx (last use) REG rcx $80 ┌──▌ t14 ref N035 (???,???) [000031] ----------- t31 = ▌ PUTARG_REG ref REG rdx N037 ( 3, 2) [000013] ----------z t13 = LCL_VAR ref V05 tmp2 u:1 rcx REG rcx ┌──▌ t13 ref N039 (???,???) [000032] ----------- t32 = ▌ PUTARG_REG ref REG rcx N041 ( 3, 2) [000015] ----------- t15 = LCL_VAR ref V02 arg2 u:1 r8 (last use) REG r8 $81 ┌──▌ t15 ref N043 (???,???) [000033] ----------- t33 = ▌ PUTARG_REG ref REG r8 N045 ( 3, 2) [000021] ----------- t21 = LCL_VAR ref V05 tmp2 u:1 rcx (last use) REG rcx ┌──▌ t21 ref N047 ( 6, 4) [000022] #----O----- t22 = ▌ IND long REG rax ┌──▌ t22 long N049 ( 7, 5) [000024] -c--------- t24 = ▌ LEA(b+72) long REG NA ┌──▌ t24 long N051 ( 9, 7) [000025] #----O----- t25 = ▌ IND long REG rax ┌──▌ t25 long N053 ( 10, 8) [000027] -c--------- t27 = ▌ LEA(b+32) long REG NA ┌──▌ t27 long N055 ( 12, 10) [000028] nc---O----- t28 = ▌ IND long REG NA ┌──▌ t31 ref arg1 in rdx ├──▌ t32 ref this in rcx ├──▌ t33 ref arg2 in r8 ├──▌ t28 long control expr N057 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName REG NA $VN.Void ------------------------------------------------------------------------------------------------------------------- Final allocation ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ TreeID LocRP# Name Type Action Reg │rax │rcx │rdx │rbx │rbp │rsi │rdi │r8 │r9 │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ 0.#0 V0 Parm Alloc rcx │ │V0 a│ │ │ │ │ │ │ │ 0.#1 V2 Parm Alloc r8 │ │V0 a│ │ │ │ │ │V2 a│ │ 1.#2 BB1 PredBB0 │ │V0 a│ │ │ │ │ │V2 a│ │ [000001] 9.#3 V0 Use Keep rcx │ │V0 a│ │ │ │ │ │V2 a│ │ 10.#4 I4 Def Alloc rdx │ │V0 a│I4 a│ │ │ │ │V2 a│ │ [000003] 11.#5 I4 Use * Keep rdx │ │V0 a│I4 i│ │ │ │ │V2 a│ │ 12.#6 V4 Def Alloc rdx │ │V0 a│V4 a│ │ │ │ │V2 a│ │ [000010] 15.#7 V4 Use * Keep rdx │ │V0 a│V4 i│ │ │ │ │V2 a│ │ 16.#8 V5 Def Alloc rdx │ │V0 a│V5 a│ │ │ │ │V2 a│ │ [000007] 21.#9 V5 Use Keep rdx │ │V0 a│V5 i│ │ │ │ │V2 a│ │ Spill rdx │ │V0 a│V5 i│ │ │ │ │V2 a│ │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ TreeID LocRP# Name Type Action Reg │rax │rcx │rdx │rbx │rbp │rsi │rdi │r8 │r9 │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ 25.#10 BB2 PredBB1 │ │ │ │ │ │ │ │ │ │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ TreeID LocRP# Name Type Action Reg │rax │rcx │rdx │rbx │rbp │rsi │rdi │r8 │r9 │ ──────────────────────────────────────────┼────┼────┼────┼────┼────┼────┼────┼────┼────┤ 31.#11 BB3 PredBB1 │ │V0 a│ │ │ │ │ │V2 a│ │ [000031] 35.#12 rdx Fixd Keep rdx │ │V0 a│ │ │ │ │ │V2 a│ │ 35.#13 V0 Use * Copy rdx │ │V0 i│V0 i│ │ │ │ │V2 a│ │ 36.#14 rdx Fixd Keep rdx │ │ │ │ │ │ │ │V2 a│ │ 36.#15 I5 Def Alloc rdx │ │ │I5 a│ │ │ │ │V2 a│ │ [000032] 39.#16 rcx Fixd Keep rcx │ │ │I5 a│ │ │ │ │V2 a│ │ 39.#17 V5 Use ReLod rcx │ │V5 a│I5 a│ │ │ │ │V2 a│ │ Keep rcx │ │V5 a│I5 a│ │ │ │ │V2 a│ │ 40.#18 rcx Fixd Keep rcx │ │V5 a│I5 a│ │ │ │ │V2 a│ │ 40.#19 I6 Def PtArg rcx │ │V5 a│I5 a│ │ │ │ │V2 a│ │ [000033] 43.#20 r8 Fixd Keep r8 │ │V5 a│I5 a│ │ │ │ │V2 a│ │ 43.#21 V2 Use * Keep r8 │ │V5 a│I5 a│ │ │ │ │V2 i│ │ 44.#22 r8 Fixd Keep r8 │ │V5 a│I5 a│ │ │ │ │ │ │ 44.#23 I7 Def Alloc r8 │ │V5 a│I5 a│ │ │ │ │I7 a│ │ [000022] 47.#24 V5 Use * Keep rcx │ │V5 i│I5 a│ │ │ │ │I7 a│ │ 48.#25 I8 Def Alloc rax │I8 a│ │I5 a│ │ │ │ │I7 a│ │ [000025] 51.#26 I8 Use * Keep rax │I8 i│ │I5 a│ │ │ │ │I7 a│ │ 52.#27 I9 Def Alloc rax │I9 a│ │I5 a│ │ │ │ │I7 a│ │ [000016] 57.#28 rdx Fixd Keep rdx │I9 a│ │I5 a│ │ │ │ │I7 a│ │ 57.#29 I5 Use * Keep rdx │I9 a│ │I5 i│ │ │ │ │I7 a│ │ 57.#30 rcx Fixd Keep rcx │I9 a│ │ │ │ │ │ │I7 a│ │ 57.#31 I6 Use * PtArg rcx │I9 a│ │ │ │ │ │ │I7 a│ │ 57.#32 r8 Fixd Keep r8 │I9 a│ │ │ │ │ │ │I7 a│ │ 57.#33 I7 Use * Keep r8 │I9 a│ │ │ │ │ │ │I7 i│ │ 57.#34 I9 Use * Keep rax │I9 i│ │ │ │ │ │ │ │ │ 58.#35 rax Kill Keep rax │ │ │ │ │ │ │ │ │ │ 58.#36 rcx Kill Keep rcx │ │ │ │ │ │ │ │ │ │ 58.#37 rdx Kill Keep rdx │ │ │ │ │ │ │ │ │ │ 58.#38 r8 Kill Keep r8 │ │ │ │ │ │ │ │ │ │ 58.#39 r9 Kill Keep r9 │ │ │ │ │ │ │ │ │ │ 58.#40 r10 Kill Keep r10 │ │ │ │ │ │ │ │ │ │ 58.#41 r11 Kill Keep r11 │ │ │ │ │ │ │ │ │ │ Recording the maximum number of concurrent spills: ---------- LSRA Stats ---------- Register selection order: ABCDEFGHIJKLMNOPQ Total Tracked Vars: 4 Total Reg Cand Vars: 4 Total number of Intervals: 9 Total number of RefPositions: 41 Total Number of spill temps created: 0 .......... BB01 [ 100.00]: SpillCount = 1, COVERS = 2, BEST_FIT = 1 BB03 [ 50.00]: REG_ORDER = 2 .......... Total SpillCount : 1 Weighted: 100.000000 Total CopyReg : 0 Weighted: 0.000000 Total ResolutionMovs : 0 Weighted: 0.000000 Total SplitEdges : 0 Weighted: 0.000000 .......... Total COVERS [# 4] : 2 Weighted: 200.000000 Total BEST_FIT [#11] : 1 Weighted: 100.000000 Total REG_ORDER [#13] : 2 Weighted: 100.000000 TUPLE STYLE DUMP WITH REGISTER ASSIGNMENTS Incoming Parameters: V00(rcx) V02(r8) BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} ===== N003. IL_OFFSET INLRT @ 0x000[E-] N005. V00(rcx) N007. STK = LEA(b+16); rcx N009. rdx = IND ; STK * N011. V04(rdx); rdx N013. V04(rdx*) $ N015. V05(rdx)R; rdx* S N017. V05(rdx) N019. CNS_INT null N021. NE ; rdx N023. JTRUE Var=Reg end of BB01: V00=rcx V02=r8 BB02 [009..00B) (return), preds={BB01} succs={} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB02: none N027. IL_OFFSET INLRT @ 0x00A[E-] N029. RETURN Var=Reg end of BB02: none BB03 [00B..013) (return), preds={BB01} succs={} ===== Predecessor for variable locations: BB01 Var=Reg beg of BB03: V00=rcx V02=r8 N033. V00(rcx*) N035. rdx = PUTARG_REG; rcx* N037. V05(rcx)R N039. rcx = PUTARG_REG; rcx N041. V02(r8*) N043. r8 = PUTARG_REG; r8* N045. V05(rcx*) N047. rax = IND ; rcx* N049. STK = LEA(b+72); rax N051. rax = IND ; STK N053. STK = LEA(b+32); rax N055. STK = IND ; STK N057. CALLV vt-ind; rdx,rcx,r8,STK Var=Reg end of BB03: none *************** Finishing PHASE Linear scan register alloc Trees after Linear scan register alloc ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i LIR BB02 [0001] 1 BB01 0.50 [009..00B) (return) i LIR BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- ------------ BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} N003 (???,???) [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR ref V00 this u:1 rcx REG rcx $80 ┌──▌ t0 ref N007 ( 2, 2) [000020] -c--------- t20 = ▌ LEA(b+16) byref REG NA ┌──▌ t20 byref N009 ( 4, 4) [000001] ---XG------ t1 = ▌ IND ref REG rdx ┌──▌ t1 ref N011 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 rdx REG rdx N013 ( 1, 1) [000004] ----------- t4 = LCL_VAR ref V04 tmp1 u:1 rdx (last use) REG rdx ┌──▌ t4 ref N015 ( 5, 4) [000010] DA--------z ▌ STORE_LCL_VAR ref V05 tmp2 d:1 rdx REG rdx N017 ( 1, 1) [000005] ----------Z t5 = LCL_VAR ref V05 tmp2 u:1 rdx REG rdx N019 ( 1, 1) [000006] -c--------- t6 = CNS_INT ref null REG NA $VN.Null ┌──▌ t5 ref ├──▌ t6 ref N021 ( 3, 3) [000007] J------N--- ▌ NE void REG NA N023 ( 5, 5) [000008] ----------- ▌ JTRUE void REG NA $VN.Void ------------ BB02 [009..00B) (return), preds={BB01} succs={} N027 (???,???) [000030] ----------- IL_OFFSET void INLRT @ 0x00A[E-] REG NA N029 ( 0, 0) [000018] ----------- RETURN void REG NA $VN.Void ------------ BB03 [00B..013) (return), preds={BB01} succs={} N033 ( 1, 1) [000014] ----------- t14 = LCL_VAR ref V00 this u:1 rcx (last use) REG rcx $80 ┌──▌ t14 ref N035 (???,???) [000031] ----------- t31 = ▌ PUTARG_REG ref REG rdx N037 ( 3, 2) [000013] ----------z t13 = LCL_VAR ref V05 tmp2 u:1 rcx REG rcx ┌──▌ t13 ref N039 (???,???) [000032] ----------- t32 = ▌ PUTARG_REG ref REG rcx N041 ( 3, 2) [000015] ----------- t15 = LCL_VAR ref V02 arg2 u:1 r8 (last use) REG r8 $81 ┌──▌ t15 ref N043 (???,???) [000033] ----------- t33 = ▌ PUTARG_REG ref REG r8 N045 ( 3, 2) [000021] ----------- t21 = LCL_VAR ref V05 tmp2 u:1 rcx (last use) REG rcx ┌──▌ t21 ref N047 ( 6, 4) [000022] #----O----- t22 = ▌ IND long REG rax ┌──▌ t22 long N049 ( 7, 5) [000024] -c--------- t24 = ▌ LEA(b+72) long REG NA ┌──▌ t24 long N051 ( 9, 7) [000025] #----O----- t25 = ▌ IND long REG rax ┌──▌ t25 long N053 ( 10, 8) [000027] -c--------- t27 = ▌ LEA(b+32) long REG NA ┌──▌ t27 long N055 ( 12, 10) [000028] nc---O----- t28 = ▌ IND long REG NA ┌──▌ t31 ref arg1 in rdx ├──▌ t32 ref this in rcx ├──▌ t33 ref arg2 in r8 ├──▌ t28 long control expr N057 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName REG NA $VN.Void ------------------------------------------------------------------------------------------------------------------- *************** In fgDebugCheckBBlist *************** In fgDebugCheckLoopTable: loop table not valid *************** Starting PHASE Place 'align' instructions *************** Finishing PHASE Place 'align' instructions [no changes] *************** In genGenerateCode() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i LIR BB02 [0001] 1 BB01 0.50 [009..00B) (return) i LIR BB03 [0002] 1 BB01 0.50 [00B..013) (return) i jmp hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- *************** Starting PHASE Generate code *************** In fgDebugCheckBBlist Finalizing stack frame Recording Var Locations at start of BB01 V00(rcx) V02(r8) Modified regs: [rax rcx rdx r8-r11] Callee-saved registers pushed: 0 [] *************** In lvaAssignFrameOffsets(FINAL_FRAME_LAYOUT) Assign V05 tmp2, size=8, stkOffs=-0x10 --- delta bump 8 for RA --- delta bump 8 for RSP frame --- virtual stack offset to actual stack offset delta is 16 -- V00 was 0, now 16 -- V01 was 8, now 24 -- V02 was 16, now 32 -- V03 was 0, now 16 -- V05 was -16, now 0 ; Final local variable assignments ; ; V00 this [V00,T00] ( 4, 3.50) ref -> rcx this class-hnd single-def ;* V01 arg1 [V01 ] ( 0, 0 ) int -> zero-ref single-def ; V02 arg2 [V02,T01] ( 3, 2.50) ref -> r8 class-hnd single-def ;# V03 OutArgs [V03 ] ( 1, 1 ) lclBlk ( 0) [rsp+00H] "OutgoingArgSpace" ; V04 tmp1 [V04,T02] ( 2, 4 ) ref -> rdx class-hnd single-def "dup spill" ; V05 tmp2 [V05,T03] ( 4, 3 ) ref -> [rsp+00H] spill-single-def ; ; Lcl frame size = 8 Mark labels for codegen BB01 : first block BB03 : branch target *************** After genMarkLabelsForCodegen() ----------------------------------------------------------------------------------------------------------------------------------------- BBnum BBid ref try hnd preds weight lp [IL range] [jump] [EH region] [flags] ----------------------------------------------------------------------------------------------------------------------------------------- BB01 [0000] 1 1 [000..009)-> BB03 ( cond ) i label LIR BB02 [0001] 1 BB01 0.50 [009..00B) (return) i LIR BB03 [0002] 1 BB01 0.50 [00B..013) (return) i label jmp hascall LIR ----------------------------------------------------------------------------------------------------------------------------------------- Setting stack level from -572662307 to 0 =============== Generating BB01 [000..009) -> BB03 (cond), preds={} succs={BB02,BB03} flags=0x00000000.20010020: i label LIR BB01 IN (2)={V00 V02 } + ByrefExposed + GcHeap OUT(3)={V00 V02 V05} + ByrefExposed + GcHeap Recording Var Locations at start of BB01 V00(rcx) V02(r8) Change life 0000000000000000 {} -> 0000000000000003 {V00 V02} V00 in reg rcx is becoming live [------] Live regs: 00000000 {} => 00000002 {rcx} New debug range: first V02 in reg r8 is becoming live [------] Live regs: 00000002 {rcx} => 00000102 {rcx r8} New debug range: first Live regs: (unchanged) 00000102 {rcx r8} GC regs: (unchanged) 00000102 {rcx r8} Byref regs: (unchanged) 00000000 {} L_M49570_BB01: Mapped BB01 to G_M49570_IG02 Label: IG02, GCvars=0000000000000000 {}, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {} Scope info: begin block BB01, IL range [000..009) Added IP mapping: 0x0000 STACK_EMPTY (G_M49570_IG02,ins#0,ofs#0) label Generating: N003 (???,???) [000029] ----------- IL_OFFSET void INLRT @ 0x000[E-] REG NA Generating: N005 ( 1, 1) [000000] ----------- t0 = LCL_VAR ref V00 this u:1 rcx REG rcx $80 ┌──▌ t0 ref Generating: N007 ( 2, 2) [000020] -c--------- t20 = ▌ LEA(b+16) byref REG NA ┌──▌ t20 byref Generating: N009 ( 4, 4) [000001] ---XG------ t1 = ▌ IND ref REG rdx IN0001: mov rdx, gword ptr [rcx+10H] GC regs: 00000102 {rcx r8} => 00000106 {rcx rdx r8} ┌──▌ t1 ref Generating: N011 ( 4, 4) [000003] DA-XG------ ▌ STORE_LCL_VAR ref V04 tmp1 d:1 rdx REG rdx GC regs: 00000106 {rcx rdx r8} => 00000102 {rcx r8} V04 in reg rdx is becoming live [000003] Live regs: 00000102 {rcx r8} => 00000106 {rcx rdx r8} Live vars: {V00 V02} => {V00 V02 V04} GC regs: 00000102 {rcx r8} => 00000106 {rcx rdx r8} Generating: N013 ( 1, 1) [000004] ----------- t4 = LCL_VAR ref V04 tmp1 u:1 rdx (last use) REG rdx ┌──▌ t4 ref Generating: N015 ( 5, 4) [000010] DA--------z ▌ STORE_LCL_VAR ref V05 tmp2 d:1 rdx REG rdx V04 in reg rdx is becoming dead [000004] Live regs: 00000106 {rcx rdx r8} => 00000102 {rcx r8} Live vars: {V00 V02 V04} => {V00 V02} GC regs: 00000106 {rcx rdx r8} => 00000102 {rcx r8} IN0002: mov gword ptr [V05 rsp], rdx V05 in reg rdx is becoming live [000010] Live regs: 00000102 {rcx r8} => 00000106 {rcx rdx r8} Live vars: {V00 V02} => {V00 V02 V05} GCvars: {} => {V05} GC regs: 00000102 {rcx r8} => 00000106 {rcx rdx r8} Generating: N017 ( 1, 1) [000005] ----------Z t5 = LCL_VAR ref V05 tmp2 u:1 rdx REG rdx Generating: N019 ( 1, 1) [000006] -c--------- t6 = CNS_INT ref null REG NA $VN.Null ┌──▌ t5 ref ├──▌ t6 ref Generating: N021 ( 3, 3) [000007] J------N--- ▌ NE void REG NA V05 in reg rdx is becoming dead [000005] Live regs: 00000106 {rcx rdx r8} => 00000102 {rcx r8} GC regs: 00000106 {rcx rdx r8} => 00000102 {rcx r8} Var V05 continuing live IN0003: test rdx, rdx Generating: N023 ( 5, 5) [000008] ----------- ▌ JTRUE void REG NA $VN.Void IN0004: jne L_M49570_BB03 Variable Live Range History Dump for BB01 V00 this: rcx [(G_M49570_IG02,ins#0,ofs#0), ...] V02 arg2: r8 [(G_M49570_IG02,ins#0,ofs#0), ...] =============== Generating BB02 [009..00B) (return), preds={BB01} succs={} flags=0x00000000.20000020: i LIR BB02 IN (0)={} OUT(0)={} Recording Var Locations at start of BB02 Change life 000000000000000B {V00 V02 V05} -> 0000000000000000 {} V00 in reg rcx is becoming dead [------] Live regs: (unchanged) 00000000 {} V02 in reg r8 is becoming dead [------] Live regs: (unchanged) 00000000 {} V05 becoming dead Live regs: (unchanged) 00000000 {} GC regs: (unchanged) 00000000 {} Byref regs: (unchanged) 00000000 {} L_M49570_BB02: Adding label due to BB weight difference: BBJ_COND BB01 with weight 100 different from BB02 with weight 50 G_M49570_IG02: ; offs=000000H, funclet=00, bbWeight=1 , byref Mapped BB02 to G_M49570_IG03 Label: IG03, GCvars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} Scope info: begin block BB02, IL range [009..00B) Added IP mapping: 0x000A STACK_EMPTY (G_M49570_IG03,ins#0,ofs#0) label Generating: N027 (???,???) [000030] ----------- IL_OFFSET void INLRT @ 0x00A[E-] REG NA Generating: N029 ( 0, 0) [000018] ----------- RETURN void REG NA $VN.Void Added IP mapping: EPILOG (G_M49570_IG03,ins#0,ofs#0) label Reserving epilog IG for block BB02 *************** After placeholder IG creation G_M49570_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M49570_IG02: ; offs=000000H, size=0011H, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB01 [0000], byref G_M49570_IG03: ; epilog placeholder, next placeholder=, BB02 [0001], epilog <-- First placeholder <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000102 {rcx r8}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M49570_IG04: ; offs=000111H, size=0000H, gcrefRegs=00000000 {} <-- Current IG Variable Live Range History Dump for BB02 V00 this: rcx [(G_M49570_IG02,ins#0,ofs#0), (G_M49570_IG02,ins#4,ofs#17)] V02 arg2: r8 [(G_M49570_IG02,ins#0,ofs#0), (G_M49570_IG02,ins#4,ofs#17)] =============== Generating BB03 [00B..013) (return), preds={BB01} succs={} flags=0x00000002.20050020: i label jmp hascall LIR BB03 IN (3)={V00 V02 V05} + ByrefExposed + GcHeap OUT(0)={ } Recording Var Locations at start of BB03 V00(rcx) V02(r8) Change life 0000000000000000 {} -> 000000000000000B {V00 V02 V05} V00 in reg rcx is becoming live [------] Live regs: 00000000 {} => 00000002 {rcx} New debug range: new var or location V02 in reg r8 is becoming live [------] Live regs: 00000002 {rcx} => 00000102 {rcx r8} New debug range: new var or location V05 becoming live Live regs: (unchanged) 00000102 {rcx r8} GC regs: (unchanged) 00000102 {rcx r8} Byref regs: (unchanged) 00000000 {} L_M49570_BB03: Mapped BB03 to G_M49570_IG04 Label: IG04, GCvars=0000000000000008 {V05}, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {} Scope info: begin block BB03, IL range [00B..013) Generating: N033 ( 1, 1) [000014] ----------- t14 = LCL_VAR ref V00 this u:1 rcx (last use) REG rcx $80 ┌──▌ t14 ref Generating: N035 (???,???) [000031] ----------- t31 = ▌ PUTARG_REG ref REG rdx V00 in reg rcx is becoming dead [000014] Live regs: 00000102 {rcx r8} => 00000100 {r8} Live vars: {V00 V02 V05} => {V02 V05} GC regs: 00000102 {rcx r8} => 00000100 {r8} IN0005: mov rdx, rcx GC regs: 00000100 {r8} => 00000104 {rdx r8} Generating: N037 ( 3, 2) [000013] ----------z t13 = LCL_VAR ref V05 tmp2 u:1 rcx REG rcx ┌──▌ t13 ref Generating: N039 (???,???) [000032] ----------- t32 = ▌ PUTARG_REG ref REG rcx IN0006: mov rcx, gword ptr [V05 rsp] V05 in reg rcx is becoming live [000013] Live regs: 00000100 {r8} => 00000102 {rcx r8} GC regs: 00000104 {rdx r8} => 00000106 {rcx rdx r8} Generating: N041 ( 3, 2) [000015] ----------- t15 = LCL_VAR ref V02 arg2 u:1 r8 (last use) REG r8 $81 ┌──▌ t15 ref Generating: N043 (???,???) [000033] ----------- t33 = ▌ PUTARG_REG ref REG r8 V02 in reg r8 is becoming dead [000015] Live regs: 00000102 {rcx r8} => 00000002 {rcx} Live vars: {V02 V05} => {V05} GC regs: 00000106 {rcx rdx r8} => 00000006 {rcx rdx} GC regs: 00000006 {rcx rdx} => 00000106 {rcx rdx r8} Generating: N045 ( 3, 2) [000021] ----------- t21 = LCL_VAR ref V05 tmp2 u:1 rcx (last use) REG rcx ┌──▌ t21 ref Generating: N047 ( 6, 4) [000022] #----O----- t22 = ▌ IND long REG rax V05 in reg rcx is becoming dead [000021] Live regs: 00000002 {rcx} => 00000000 {} Live vars: {V05} => {} GCvars: {V05} => {} GC regs: 00000106 {rcx rdx r8} => 00000104 {rdx r8} IN0007: mov rax, qword ptr [rcx] ┌──▌ t22 long Generating: N049 ( 7, 5) [000024] -c--------- t24 = ▌ LEA(b+72) long REG NA ┌──▌ t24 long Generating: N051 ( 9, 7) [000025] #----O----- t25 = ▌ IND long REG rax IN0008: mov rax, qword ptr [rax+48H] ┌──▌ t25 long Generating: N053 ( 10, 8) [000027] -c--------- t27 = ▌ LEA(b+32) long REG NA ┌──▌ t27 long Generating: N055 ( 12, 10) [000028] nc---O----- t28 = ▌ IND long REG NA ┌──▌ t31 ref arg1 in rdx ├──▌ t32 ref this in rcx ├──▌ t33 ref arg2 in r8 ├──▌ t28 long control expr Generating: N057 ( 39, 25) [000016] --CXGO----- ▌ CALLV vt-ind void hackishModuleName.hackishMethodName REG NA $VN.Void GC regs: 00000104 {rdx r8} => 00000100 {r8} GC regs: 00000100 {r8} => 00000000 {} Added IP mapping: EPILOG (G_M49570_IG04,ins#4,ofs#14) label Reserving epilog IG for block BB03 G_M49570_IG04: ; offs=000111H, funclet=00, bbWeight=0.50, gcvars, byref *************** After placeholder IG creation G_M49570_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M49570_IG02: ; offs=000000H, size=0011H, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB01 [0000], byref G_M49570_IG03: ; epilog placeholder, next placeholder=IG05 , BB02 [0001], epilog <-- First placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000102 {rcx r8}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M49570_IG04: ; offs=000111H, size=000EH, gcVars=0000000000000008 {V05}, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB03 [0002], gcvars, byref G_M49570_IG05: ; epilog placeholder, next placeholder=, BB03 [0002], epilog, extend <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000102 {rcx r8}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000008 {V05}, InitGCrefRegs=00000102 {rcx r8}, InitByrefRegs=00000000 {} Variable Live Range History Dump for BB03 V00 this: rcx [(G_M49570_IG04,ins#0,ofs#0), (G_M49570_IG04,ins#0,ofs#0)] V02 arg2: r8 [(G_M49570_IG04,ins#0,ofs#0), (G_M49570_IG04,ins#2,ofs#7)] Liveness not changing: 0000000000000000 {} # compCycleEstimate = 53, compSizeEstimate = 38 System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this ; Final local variable assignments ; ; V00 this [V00,T00] ( 4, 3.50) ref -> rcx this class-hnd single-def ;* V01 arg1 [V01 ] ( 0, 0 ) int -> zero-ref single-def ; V02 arg2 [V02,T01] ( 3, 2.50) ref -> r8 class-hnd single-def ;# V03 OutArgs [V03 ] ( 1, 1 ) lclBlk ( 0) [rsp+00H] "OutgoingArgSpace" ; V04 tmp1 [V04,T02] ( 2, 4 ) ref -> rdx class-hnd single-def "dup spill" ; V05 tmp2 [V05,T03] ( 4, 3 ) ref -> [rsp+00H] spill-single-def ; ; Lcl frame size = 8 *************** Before prolog / epilog generation G_M49570_IG01: ; func=00, offs=000000H, size=0000H, gcrefRegs=00000000 {} <-- Prolog IG G_M49570_IG02: ; offs=000000H, size=0011H, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB01 [0000], byref G_M49570_IG03: ; epilog placeholder, next placeholder=IG05 , BB02 [0001], epilog <-- First placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000102 {rcx r8}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000000 {}, InitGCrefRegs=00000000 {}, InitByrefRegs=00000000 {} G_M49570_IG04: ; offs=000111H, size=000EH, gcVars=0000000000000008 {V05}, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB03 [0002], gcvars, byref G_M49570_IG05: ; epilog placeholder, next placeholder=, BB03 [0002], epilog, extend <-- Last placeholder ; PrevGCVars=0000000000000000 {}, PrevGCrefRegs=00000102 {rcx r8}, PrevByrefRegs=00000000 {} ; InitGCVars=0000000000000008 {V05}, InitGCrefRegs=00000102 {rcx r8}, InitByrefRegs=00000000 {} Recording Var Locations at start of BB01 V00(rcx) V02(r8) *************** In genFnProlog() Added IP mapping to front: PROLOG (G_M49570_IG01,ins#0,ofs#0) label __prolog: New debug range: first New debug range: first New debug range: first IN0009: push rax *************** In genFnPrologCalleeRegArgs() for int regs *************** In genEnregisterIncomingStackArgs() 1 tracked GC refs are at stack offsets 0000 ... 0008 G_M49570_IG01: ; offs=000000H, funclet=00, bbWeight=1 , gcvars, byref, nogc *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000000 {}, gcRegGCrefSetCur=00000000 {}, gcRegByrefSetCur=00000000 {} IN000a: add rsp, 8 IN000b: ret G_M49570_IG03: ; offs=000011H, funclet=00, bbWeight=0.50, byref, epilog, nogc *************** In genFnEpilog() __epilog: gcVarPtrSetCur=0000000000000008 {V05}, gcRegGCrefSetCur=00000102 {rcx r8}, gcRegByrefSetCur=00000000 {} IN000c: add rsp, 8 Call: GCvars=0000000000000008 {V05}, gcrefRegs=00000000 {}, byrefRegs=00000000 {} IN000d: tail.jmp [rax+20H]System.Xml.Schema.XmlSchemaObject:hackishMethodName G_M49570_IG05: ; offs=00011FH, funclet=00, bbWeight=0.50, epilog, nogc, extend 0 prologs, 2 epilogs, 0 funclet prologs, 0 funclet epilogs *************** After prolog / epilog generation G_M49570_IG01: ; func=00, offs=000000H, size=0001H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, nogc <-- Prolog IG G_M49570_IG02: ; offs=000001H, size=0011H, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB01 [0000], byref G_M49570_IG03: ; offs=000012H, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc G_M49570_IG04: ; offs=000017H, size=000EH, gcVars=0000000000000008 {V05}, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB03 [0002], gcvars, byref G_M49570_IG05: ; offs=000025H, size=0008H, epilog, nogc, extend *************** In emitJumpDistBind() Emitter Jump List: IG02 IN0004 jne[6] -> IG04 total jump count: 1 Binding: IN0004: 000000 jne L_M49570_BB03 Binding L_M49570_BB03 to G_M49570_IG04 Estimate of fwd jump [F87CEC74/004]: 000C -> 0017 = 0009 Shrinking jump [F87CEC74/004] Adjusted offset of BB03 from 0012 to 000E Adjusted offset of BB04 from 0017 to 0013 Adjusted offset of BB05 from 0025 to 0021 Total shrinkage = 4, min extra jump size = 4294967295 *************** Finishing PHASE Generate code *************** Starting PHASE Emit code Hot code size = 0x29 bytes Cold code size = 0x0 bytes reserveUnwindInfo(isFunclet=false, isColdCode=false, unwindSize=0x6) *************** In emitEndCodeGen() Converting emitMaxStackDepth from bytes (0) to elements (0) *************************************************************************** Instructions as they come out of the scheduler G_M49570_IG01: ; func=00, offs=000000H, size=0001H, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, nogc <-- Prolog IG IN0009: 000000 50 push rax ;; size=1 bbWeight=1 PerfScore 1.00 G_M49570_IG02: ; func=00, offs=000001H, size=000DH, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB01 [0000], byref, isz ; gcrRegs +[rcx r8] IN0001: 000001 488B5110 mov rdx, gword ptr [rcx+10H] ; gcrRegs +[rdx] IN0002: 000005 48891424 mov gword ptr [rsp], rdx ; GC ptr vars +{V05} IN0003: 000009 4885D2 test rdx, rdx IN0004: 00000C 7505 jne SHORT G_M49570_IG04 ;; size=13 bbWeight=1 PerfScore 4.25 G_M49570_IG03: ; func=00, offs=00000EH, size=0005H, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc ; gcrRegs -[rcx rdx r8] ; GC ptr vars -{V05} IN000a: 00000E 4883C408 add rsp, 8 IN000b: 000012 C3 ret ;; size=5 bbWeight=0.50 PerfScore 0.62 G_M49570_IG04: ; func=00, offs=000013H, size=000EH, gcVars=0000000000000008 {V05}, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB03 [0002], gcvars, byref ; gcrRegs +[rcx r8] ; GC ptr vars +{V05} IN0005: 000013 488BD1 mov rdx, rcx ; gcrRegs +[rdx] IN0006: 000016 488B0C24 mov rcx, gword ptr [rsp] IN0007: 00001A 488B01 mov rax, qword ptr [rcx] IN0008: 00001D 488B4048 mov rax, qword ptr [rax+48H] ;; size=14 bbWeight=0.50 PerfScore 2.62 G_M49570_IG05: ; func=00, offs=000021H, size=0008H, epilog, nogc, extend IN000c: 000021 4883C408 add rsp, 8 IN000d: 000025 48FF6020 tail.jmp [rax+20H]System.Xml.Schema.XmlSchemaObject:hackishMethodName ;; size=8 bbWeight=0.50 PerfScore 1.12Allocated method code size = 41 , actual size = 41, unused size = 0 ; Total bytes of code 41, prolog size 1, PerfScore 13.73, instruction count 13, allocated bytes for code 41 (MethodHash=a7cc3e5d) for method System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this ; ============================================================ *************** After end code gen, before unwindEmit() G_M49570_IG01: ; func=00, offs=000000H, size=0001H, bbWeight=1 PerfScore 1.00, gcVars=0000000000000000 {}, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, gcvars, byref, nogc <-- Prolog IG IN0009: 000000 push rax G_M49570_IG02: ; offs=000001H, size=000DH, bbWeight=1 PerfScore 4.25, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB01 [0000], byref, isz IN0001: 000001 mov rdx, gword ptr [rcx+10H] IN0002: 000005 mov gword ptr [V05 rsp], rdx IN0003: 000009 test rdx, rdx IN0004: 00000C jne SHORT G_M49570_IG04 G_M49570_IG03: ; offs=00000EH, size=0005H, bbWeight=0.50 PerfScore 0.62, gcrefRegs=00000000 {}, byrefRegs=00000000 {}, byref, epilog, nogc IN000a: 00000E add rsp, 8 IN000b: 000012 ret G_M49570_IG04: ; offs=000013H, size=000EH, bbWeight=0.50 PerfScore 2.62, gcVars=0000000000000008 {V05}, gcrefRegs=00000102 {rcx r8}, byrefRegs=00000000 {}, BB03 [0002], gcvars, byref IN0005: 000013 mov rdx, rcx IN0006: 000016 mov rcx, gword ptr [V05 rsp] IN0007: 00001A mov rax, qword ptr [rcx] IN0008: 00001D mov rax, qword ptr [rax+48H] G_M49570_IG05: ; offs=000021H, size=0008H, bbWeight=0.50 PerfScore 1.12, epilog, nogc, extend IN000c: 000021 add rsp, 8 IN000d: 000025 tail.jmp [rax+20H]System.Xml.Schema.XmlSchemaObject:hackishMethodName *************** Finishing PHASE Emit code *************** Starting PHASE Emit GC+EH tables Unwind Info: >> Start offset : 0x000000 (not in unwind data) >> End offset : 0x000029 (not in unwind data) Version : 1 Flags : 0x00 SizeOfProlog : 0x01 CountOfUnwindCodes: 1 FrameRegister : none (0) FrameOffset : N/A (no FrameRegister) (Value=0) UnwindCodes : CodeOffset: 0x01 UnwindOp: UWOP_ALLOC_SMALL (2) OpInfo: 0 * 8 + 8 = 8 = 0x08 allocUnwindInfo(pHotCode=0x0000020CF87B5180, pColdCode=0x0000000000000000, startOffset=0x0, endOffset=0x29, unwindSize=0x6, pUnwindBlock=0x0000020CF87BD79A, funKind=0 (main function)) *************** In genIPmappingGen() IP mapping count : 5 IL offs PROLOG : 0x00000000 ( STACK_EMPTY ) IL offs 0x0000 : 0x00000001 ( STACK_EMPTY ) IL offs 0x000A : 0x0000000E ( STACK_EMPTY ) IL offs EPILOG : 0x0000000E ( STACK_EMPTY ) IL offs EPILOG : 0x00000021 ( STACK_EMPTY ) *************** In genSetScopeInfo() VarLocInfo count is 7 ; Variable debug info: 5 live ranges, 3 vars for method System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this 0( UNKNOWN) : From 00000000h to 0000000Eh, in rcx 0( UNKNOWN) : From 00000013h to 00000014h, in rcx 1( UNKNOWN) : From 00000000h to 00000001h, in rdx 2( UNKNOWN) : From 00000000h to 0000000Eh, in r8 2( UNKNOWN) : From 00000013h to 0000001Ah, in r8 VARIABLE LIVE RANGES: V00 this: rcx [1, E); rcx [13, 13) V02 arg2: r8 [1, E); r8 [13, 1A) *************** In gcInfoBlockHdrSave() Set code length to 41. Set ReturnKind to Scalar. Set Outgoing stack arg area size to 0. Stack slot id for offset 0 (0x0) (sp) = 0. Register slot id for reg rcx = 1. Register slot id for reg r8 = 2. Register slot id for reg rdx = 3. Set state of slot 0 at instr offset 0x9 to Live. Set state of slot 0 at instr offset 0xe to Dead. Set state of slot 0 at instr offset 0x13 to Live. Set state of slot 0 at instr offset 0x29 to Dead. Set state of slot 1 at instr offset 0x1 to Live. Set state of slot 2 at instr offset 0x1 to Live. Set state of slot 3 at instr offset 0x5 to Live. Set state of slot 1 at instr offset 0xe to Dead. Set state of slot 3 at instr offset 0xe to Dead. Set state of slot 2 at instr offset 0xe to Dead. Set state of slot 1 at instr offset 0x13 to Live. Set state of slot 2 at instr offset 0x13 to Live. Set state of slot 3 at instr offset 0x16 to Live. Set state of slot 1 at instr offset 0x29 to Dead. Set state of slot 3 at instr offset 0x29 to Dead. Set state of slot 2 at instr offset 0x29 to Dead. Defining interruptible range: [0x1, 0xe). Defining interruptible range: [0x13, 0x21). *************** Finishing PHASE Emit GC+EH tables Method code size: 41 Allocations for System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this (MethodHash=a7cc3e5d) count: 683, size: 71792, max = 3272 allocateMemory: 131072, nraUsed: 74520 Alloc'd bytes by kind: kind | size | pct ---------------------+------------+-------- AssertionProp | 6668 | 9.29% ASTNode | 4320 | 6.02% InstDesc | 3192 | 4.45% ImpStack | 432 | 0.60% BasicBlock | 1464 | 2.04% CallArgs | 264 | 0.37% FlowList | 112 | 0.16% TreeStatementList | 0 | 0.00% SiScope | 0 | 0.00% DominatorMemory | 192 | 0.27% LSRA | 5076 | 7.07% LSRA_Interval | 800 | 1.11% LSRA_RefPosition | 3024 | 4.21% Reachability | 104 | 0.14% SSA | 448 | 0.62% ValueNumber | 12828 | 17.87% LvaTable | 2072 | 2.89% UnwindInfo | 0 | 0.00% hashBv | 120 | 0.17% bitset | 120 | 0.17% FixedBitVect | 16 | 0.02% Generic | 1354 | 1.89% LocalAddressVisitor | 0 | 0.00% FieldSeqStore | 144 | 0.20% MemorySsaMap | 40 | 0.06% MemoryPhiArg | 0 | 0.00% CSE | 1504 | 2.09% GC | 2960 | 4.12% CorTailCallInfo | 0 | 0.00% Inlining | 896 | 1.25% ArrayStack | 0 | 0.00% DebugInfo | 360 | 0.50% DebugOnly | 20191 | 28.12% Codegen | 848 | 1.18% LoopOpt | 48 | 0.07% LoopClone | 0 | 0.00% LoopHoist | 0 | 0.00% Unknown | 219 | 0.31% RangeCheck | 0 | 0.00% CopyProp | 776 | 1.08% SideEffects | 0 | 0.00% ObjectAllocator | 0 | 0.00% VariableLiveRanges | 976 | 1.36% ClassLayout | 0 | 0.00% TailMergeThrows | 0 | 0.00% EarlyProp | 0 | 0.00% ZeroInit | 224 | 0.31% Pgo | 0 | 0.00% ****** DONE compiling System.Xml.Schema.XmlSchemaObjectCollection:OnInsert(int,System.Object):this Using jit(C:\dev\dotnet\runtime3\artifacts\tests\coreclr\windows.x64.Checked\Tests\Core_Root\clrjit.dll) with input (C:\dev\dotnet\spmi\mch\3f5e4630-b29a-4aeb-bab7-07bdff43a156.windows.x64\benchmarks.run.windows.x64.checked.mch) indexCount=1 (3299) Jit startup took 3.122000ms Loaded 1 Jitted 1 FailedCompile 0 Excluded 0 Missing 0 Total time: 72.387900ms