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khushal1996khushal1996
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Enable the accelerated instructions for conversion for X86
1 parent 2367f40 commit 07f6b77

4 files changed

Lines changed: 25 additions & 29 deletions

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‎src/coreclr/jit/compiler.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3172,7 +3172,7 @@ class Compiler
31723172
GenTree* op3,
31733173
CorInfoType simdBaseJitType,
31743174
unsigned simdSize);
3175-
#if defined(TARGET_AMD64)
3175+
#if defined(TARGET_XARCH)
31763176
GenTree* gtNewSimdCvtNode(var_types type,
31773177
GenTree* op1,
31783178
NamedIntrinsic hwIntrinsicID,
@@ -3184,7 +3184,7 @@ class Compiler
31843184
var_types sourceType,
31853185
var_types targetType,
31863186
unsigned simdSize);
3187-
#endif //TARGET_AMD64
3187+
#endif //TARGET_XARCH
31883188
GenTree* gtNewSimdCreateBroadcastNode(
31893189
var_types type, GenTree* op1, CorInfoType simdBaseJitType, unsigned simdSize);
31903190

‎src/coreclr/jit/gentree.cpp‎

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -21251,7 +21251,7 @@ GenTree* Compiler::gtNewSimdCeilNode(var_types type, GenTree* op1, CorInfoType s
2125121251
return gtNewSimdHWIntrinsicNode(type, op1, intrinsic, simdBaseJitType, simdSize);
2125221252
}
2125321253

21254-
#if defined(TARGET_AMD64)
21254+
#if defined(TARGET_XARCH)
2125521255
GenTreeVecCon* Compiler::gtCvtCtrlTbl(var_types type, var_types sourceType, var_types targetType, unsigned simdSize)
2125621256
{
2125721257
assert(IsBaselineSimdIsaSupportedDebugOnly());
@@ -21350,13 +21350,24 @@ GenTree* Compiler::gtNewSimdCvtNode(var_types type,
2135021350

2135121351
if (varTypeIsSigned(simdTargetBaseType))
2135221352
{
21353-
ssize_t actualMaxVal = (varTypeIsInt(simdTargetBaseType)) ? INT32_MAX : INT64_MAX;
21354-
21355-
GenTree* maxVal = gtNewDconNode(static_cast<double>(actualMaxVal), simdSourceBaseType);
21356-
21357-
maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize);
21358-
GenTree* maxValDup = gtNewSimdCreateBroadcastNode(type, gtNewIconNode(actualMaxVal, simdTargetBaseType),
21359-
simdTargetBaseJitType, simdSize);
21353+
GenTree* maxVal;
21354+
GenTree* maxValDup;
21355+
if (varTypeIsLong(simdTargetBaseType))
21356+
{
21357+
long long actualMaxVal = INT64_MAX;
21358+
maxVal = gtNewDconNode(static_cast<double>(actualMaxVal), simdSourceBaseType);
21359+
maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize);
21360+
maxValDup =
21361+
gtNewSimdCreateBroadcastNode(type, gtNewLconNode(actualMaxVal), simdTargetBaseJitType, simdSize);
21362+
}
21363+
else
21364+
{
21365+
ssize_t actualMaxVal = INT32_MAX;
21366+
maxVal = gtNewDconNode(static_cast<double>(actualMaxVal), simdSourceBaseType);
21367+
maxVal = gtNewSimdCreateBroadcastNode(type, maxVal, simdSourceBaseJitType, simdSize);
21368+
maxValDup = gtNewSimdCreateBroadcastNode(type, gtNewIconNode(actualMaxVal, simdTargetBaseType),
21369+
simdTargetBaseJitType, simdSize);
21370+
}
2136021371

2136121372
// we will be using the input value twice
2136221373
GenTree* fixupValDup = fgMakeMultiUse(&fixupVal);
@@ -21375,7 +21386,7 @@ GenTree* Compiler::gtNewSimdCvtNode(var_types type,
2137521386
return gtNewSimdHWIntrinsicNode(type, fixupVal, hwIntrinsicID, simdSourceBaseJitType, simdSize);
2137621387
}
2137721388
}
21378-
#endif // TARGET_AMD64
21389+
#endif // TARGET_XARCH
2137921390

2138021391
GenTree* Compiler::gtNewSimdCmpOpNode(
2138121392
genTreeOps op, var_types type, GenTree* op1, GenTree* op2, CorInfoType simdBaseJitType, unsigned simdSize)

‎src/coreclr/jit/hwintrinsicxarch.cpp‎

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1446,7 +1446,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
14461446
{
14471447
assert(sig->numArgs == 1);
14481448
assert(simdBaseType == TYP_DOUBLE);
1449-
#if defined(TARGET_AMD64)
14501449
if (IsBaselineVector512IsaSupportedOpportunistically())
14511450
{
14521451
op1 = impSIMDPopStack();
@@ -1457,7 +1456,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
14571456

14581457
retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_LONG, simdBaseJitType, simdSize);
14591458
}
1460-
#endif
14611459
break;
14621460
}
14631461

@@ -1467,7 +1465,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
14671465
{
14681466
assert(sig->numArgs == 1);
14691467
assert(simdBaseType == TYP_FLOAT);
1470-
#if defined(TARGET_AMD64)
14711468
if (IsBaselineVector512IsaSupportedOpportunistically())
14721469
{
14731470
op1 = impSIMDPopStack();
@@ -1477,7 +1474,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
14771474

14781475
retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_UINT, simdBaseJitType, simdSize);
14791476
}
1480-
#endif
1477+
#
14811478
break;
14821479
}
14831480

@@ -1487,7 +1484,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
14871484
{
14881485
assert(sig->numArgs == 1);
14891486
assert(simdBaseType == TYP_DOUBLE);
1490-
#if defined(TARGET_AMD64)
14911487
if (IsBaselineVector512IsaSupportedOpportunistically())
14921488
{
14931489
op1 = impSIMDPopStack();
@@ -1497,7 +1493,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
14971493

14981494
retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_ULONG, simdBaseJitType, simdSize);
14991495
}
1500-
#endif
15011496
break;
15021497
}
15031498

@@ -1507,7 +1502,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
15071502
{
15081503
assert(sig->numArgs == 1);
15091504
assert(simdBaseType == TYP_FLOAT);
1510-
#if defined(TARGET_AMD64)
15111505
if (IsBaselineVector512IsaSupportedOpportunistically())
15121506
{
15131507
op1 = impSIMDPopStack();
@@ -1517,7 +1511,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
15171511

15181512
retNode = gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_INT, simdBaseJitType, simdSize);
15191513
}
1520-
#endif
15211514
break;
15221515
}
15231516

‎src/coreclr/jit/simdashwintrinsic.cpp‎

Lines changed: 2 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -532,12 +532,12 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
532532
case NI_VectorT_ConvertToUInt32:
533533
case NI_VectorT_ConvertToUInt64:
534534
{
535-
#ifdef TARGET_AMD64
535+
#ifdef TARGET_XARCH
536536
if (IsBaselineVector512IsaSupportedOpportunistically())
537537
{
538538
break;
539539
}
540-
#endif // TARGET_AMD64
540+
#endif // TARGET_XARCH
541541
return nullptr;
542542
}
543543

@@ -1181,7 +1181,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
11811181
{
11821182
assert(sig->numArgs == 1);
11831183
assert(simdBaseType == TYP_DOUBLE);
1184-
#if defined(TARGET_AMD64)
11851184
if (IsBaselineVector512IsaSupportedOpportunistically())
11861185
{
11871186
NamedIntrinsic intrinsic =
@@ -1191,15 +1190,13 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
11911190

11921191
return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_LONG, simdBaseJitType, simdSize);
11931192
}
1194-
#endif
11951193
return nullptr;
11961194
}
11971195

11981196
case NI_VectorT_ConvertToUInt32:
11991197
{
12001198
assert(sig->numArgs == 1);
12011199
assert(simdBaseType == TYP_FLOAT);
1202-
#if defined(TARGET_AMD64)
12031200
if (IsBaselineVector512IsaSupportedOpportunistically())
12041201
{
12051202
NamedIntrinsic intrinsic =
@@ -1209,15 +1206,13 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
12091206

12101207
return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_UINT, simdBaseJitType, simdSize);
12111208
}
1212-
#endif
12131209
return nullptr;
12141210
}
12151211

12161212
case NI_VectorT_ConvertToUInt64:
12171213
{
12181214
assert(sig->numArgs == 1);
12191215
assert(simdBaseType == TYP_DOUBLE);
1220-
#if defined(TARGET_AMD64)
12211216
if (IsBaselineVector512IsaSupportedOpportunistically())
12221217
{
12231218
NamedIntrinsic intrinsic =
@@ -1227,14 +1222,12 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
12271222

12281223
return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_ULONG, simdBaseJitType, simdSize);
12291224
}
1230-
#endif
12311225
return nullptr;
12321226
}
12331227

12341228
case NI_VectorT_ConvertToInt32:
12351229
{
12361230
assert(simdBaseType == TYP_FLOAT);
1237-
#if defined(TARGET_AMD64)
12381231
if (IsBaselineVector512IsaSupportedOpportunistically())
12391232
{
12401233
NamedIntrinsic intrinsic =
@@ -1244,7 +1237,6 @@ GenTree* Compiler::impSimdAsHWIntrinsicSpecial(NamedIntrinsic intrinsic,
12441237

12451238
return gtNewSimdCvtNode(retType, op1, intrinsic, CORINFO_TYPE_INT, simdBaseJitType, simdSize);
12461239
}
1247-
#endif
12481240
return nullptr;
12491241
}
12501242

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